O3: When squashing, restore the macroop that should be used for fetching.
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ec204f003c
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0e6dc00497
4 changed files with 20 additions and 10 deletions
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@ -135,6 +135,7 @@ struct TimeBufStruct {
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bool branchTaken;
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Addr mispredPC;
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TheISA::PCState nextPC;
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DynInstPtr squashInst;
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unsigned branchCount;
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};
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@ -280,6 +280,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
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toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
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toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
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toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
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toFetch->decodeInfo[tid].squashInst = inst;
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InstSeqNum squash_seq_num = inst->seqNum;
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@ -332,13 +332,15 @@ class DefaultFetch
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}
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/** Squashes a specific thread and resets the PC. */
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inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
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inline void doSquash(const TheISA::PCState &newPC,
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const DynInstPtr squashInst, ThreadID tid);
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/** Squashes a specific thread and resets the PC. Also tells the CPU to
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* remove any instructions between fetch and decode that should be sqaushed.
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*/
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void squashFromDecode(const TheISA::PCState &newPC,
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const InstSeqNum &seq_num, ThreadID tid);
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const DynInstPtr squashInst,
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const InstSeqNum seq_num, ThreadID tid);
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/** Checks if a thread is stalled. */
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bool checkStall(ThreadID tid) const;
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@ -352,8 +354,8 @@ class DefaultFetch
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* remove any instructions that are not in the ROB. The source of this
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* squash should be the commit stage.
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*/
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void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
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DynInstPtr &squashInst, ThreadID tid);
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void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
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DynInstPtr squashInst, ThreadID tid);
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/** Ticks the fetch stage, processing all inputs signals and fetching
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* as many instructions as possible.
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@ -746,14 +746,18 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
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template <class Impl>
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inline void
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DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
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DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
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const DynInstPtr squashInst, ThreadID tid)
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{
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DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
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tid, newPC);
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pc[tid] = newPC;
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fetchOffset[tid] = 0;
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macroop[tid] = NULL;
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if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
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macroop[tid] = squashInst->macroop;
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else
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macroop[tid] = NULL;
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predecoder.reset();
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// Clear the icache miss if it's outstanding.
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@ -786,11 +790,12 @@ DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
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template<class Impl>
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void
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DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
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const InstSeqNum &seq_num, ThreadID tid)
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const DynInstPtr squashInst,
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const InstSeqNum seq_num, ThreadID tid)
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{
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DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
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doSquash(newPC, tid);
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doSquash(newPC, squashInst, tid);
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// Tell the CPU to remove any instructions that are in flight between
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// fetch and decode.
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@ -866,12 +871,12 @@ DefaultFetch<Impl>::updateFetchStatus()
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template <class Impl>
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void
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DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
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const InstSeqNum &seq_num, DynInstPtr &squashInst,
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const InstSeqNum seq_num, DynInstPtr squashInst,
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ThreadID tid)
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{
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DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
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doSquash(newPC, tid);
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doSquash(newPC, squashInst, tid);
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// Tell the CPU to remove any instructions that are not in the ROB.
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cpu->removeInstsNotInROB(tid);
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@ -1052,6 +1057,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
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DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
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// Squash unless we're already squashing
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squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
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fromDecode->decodeInfo[tid].squashInst,
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fromDecode->decodeInfo[tid].doneSeqNum,
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tid);
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