fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
This commit is contained in:
parent
b7292a1713
commit
0dfc29a023
9 changed files with 165 additions and 39 deletions
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@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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self.readfile = mdesc.script()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.bridge = Bridge(fix_partial_write_b=True)
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.bridge.side_b = self.membus.port
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@ -43,20 +43,24 @@
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Bridge::BridgePort::BridgePort(const std::string &_name,
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Bridge::BridgePort::BridgePort(const std::string &_name,
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Bridge *_bridge, BridgePort *_otherPort,
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Bridge *_bridge, BridgePort *_otherPort,
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int _delay, int _queueLimit)
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int _delay, int _queueLimit,
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bool fix_partial_write)
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: Port(_name), bridge(_bridge), otherPort(_otherPort),
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: Port(_name), bridge(_bridge), otherPort(_otherPort),
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delay(_delay), outstandingResponses(0),
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delay(_delay), fixPartialWrite(fix_partial_write),
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queueLimit(_queueLimit), sendEvent(this)
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outstandingResponses(0), queueLimit(_queueLimit), sendEvent(this)
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{
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{
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}
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}
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Bridge::Bridge(const std::string &n, int qsa, int qsb,
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Bridge::Bridge(const std::string &n, int qsa, int qsb,
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Tick _delay, int write_ack)
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Tick _delay, int write_ack, bool fix_partial_write_a,
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bool fix_partial_write_b)
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: MemObject(n),
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: MemObject(n),
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portA(n + "-portA", this, &portB, _delay, qsa),
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portA(n + "-portA", this, &portB, _delay, qsa, fix_partial_write_a),
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portB(n + "-portB", this, &portA, _delay, qsa),
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portB(n + "-portB", this, &portA, _delay, qsa, fix_partial_write_b),
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ackWrites(write_ack)
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ackWrites(write_ack)
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{
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{
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if (ackWrites)
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panic("No support for acknowledging writes\n");
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}
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}
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Port *
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Port *
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@ -82,7 +86,10 @@ Bridge::init()
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{
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{
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// Make sure that both sides are connected to.
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// Make sure that both sides are connected to.
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if (portA.getPeer() == NULL || portB.getPeer() == NULL)
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if (portA.getPeer() == NULL || portB.getPeer() == NULL)
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panic("Both ports of bus bridge are not connected to a bus.\n");
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fatal("Both ports of bus bridge are not connected to a bus.\n");
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if (portA.peerBlockSize() != portB.peerBlockSize())
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fatal("Busses don't have the same block size... Not supported.\n");
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}
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}
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@ -107,8 +114,10 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt)
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bool
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bool
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Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
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Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
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{
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{
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if (queueFull())
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if (queueFull()) {
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DPRINTF(BusBridge, "Queue full, returning false\n");
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return false;
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return false;
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}
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if (pkt->isResponse()) {
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if (pkt->isResponse()) {
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// This is a response for a request we forwarded earlier. The
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// This is a response for a request we forwarded earlier. The
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@ -149,6 +158,7 @@ Bridge::BridgePort::trySend()
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assert(!sendQueue.empty());
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assert(!sendQueue.empty());
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bool was_full = queueFull();
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bool was_full = queueFull();
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int pbs = peerBlockSize();
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PacketBuffer *buf = sendQueue.front();
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PacketBuffer *buf = sendQueue.front();
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@ -156,10 +166,18 @@ Bridge::BridgePort::trySend()
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PacketPtr pkt = buf->pkt;
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PacketPtr pkt = buf->pkt;
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pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set
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if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite &&
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pkt->getOffset(pbs) && pkt->getSize() != pbs) {
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buf->partialWriteFix(this);
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pkt = buf->pkt;
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}
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DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
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DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
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buf->origSrc, pkt->getDest(), pkt->getAddr());
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buf->origSrc, pkt->getDest(), pkt->getAddr());
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pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set
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if (sendTiming(pkt)) {
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if (sendTiming(pkt)) {
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// send successful
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// send successful
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sendQueue.pop_front();
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sendQueue.pop_front();
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@ -191,6 +209,7 @@ Bridge::BridgePort::trySend()
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} else {
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} else {
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DPRINTF(BusBridge, " unsuccessful\n");
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DPRINTF(BusBridge, " unsuccessful\n");
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buf->undoPartialWriteFix();
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}
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}
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}
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}
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@ -248,6 +267,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
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Param<int> queue_size_b;
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Param<int> queue_size_b;
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Param<Tick> delay;
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Param<Tick> delay;
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Param<bool> write_ack;
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Param<bool> write_ack;
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Param<bool> fix_partial_write_a;
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Param<bool> fix_partial_write_b;
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END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
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END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
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@ -256,14 +277,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
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INIT_PARAM(queue_size_a, "The size of the queue for data coming into side a"),
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INIT_PARAM(queue_size_a, "The size of the queue for data coming into side a"),
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INIT_PARAM(queue_size_b, "The size of the queue for data coming into side b"),
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INIT_PARAM(queue_size_b, "The size of the queue for data coming into side b"),
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INIT_PARAM(delay, "The miminum delay to cross this bridge"),
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INIT_PARAM(delay, "The miminum delay to cross this bridge"),
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INIT_PARAM(write_ack, "Acknowledge any writes that are received.")
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INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
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INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
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INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
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END_INIT_SIM_OBJECT_PARAMS(Bridge)
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END_INIT_SIM_OBJECT_PARAMS(Bridge)
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CREATE_SIM_OBJECT(Bridge)
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CREATE_SIM_OBJECT(Bridge)
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{
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{
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return new Bridge(getInstanceName(), queue_size_a, queue_size_b, delay,
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return new Bridge(getInstanceName(), queue_size_a, queue_size_b, delay,
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write_ack);
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write_ack, fix_partial_write_a, fix_partial_write_b);
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}
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}
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REGISTER_SIM_OBJECT("Bridge", Bridge)
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REGISTER_SIM_OBJECT("Bridge", Bridge)
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@ -66,6 +66,8 @@ class Bridge : public MemObject
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/** Minimum delay though this bridge. */
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/** Minimum delay though this bridge. */
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Tick delay;
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Tick delay;
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bool fixPartialWrite;
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class PacketBuffer : public Packet::SenderState {
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class PacketBuffer : public Packet::SenderState {
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public:
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public:
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@ -75,10 +77,13 @@ class Bridge : public MemObject
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short origSrc;
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short origSrc;
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bool expectResponse;
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bool expectResponse;
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bool partialWriteFixed;
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PacketPtr oldPkt;
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PacketBuffer(PacketPtr _pkt, Tick t)
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PacketBuffer(PacketPtr _pkt, Tick t)
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: ready(t), pkt(_pkt),
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: ready(t), pkt(_pkt),
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origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()),
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origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()),
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expectResponse(_pkt->needsResponse())
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expectResponse(_pkt->needsResponse()), partialWriteFixed(false)
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{
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{
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if (!pkt->isResponse())
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if (!pkt->isResponse())
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pkt->senderState = this;
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pkt->senderState = this;
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@ -89,7 +94,46 @@ class Bridge : public MemObject
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assert(pkt->senderState == this);
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assert(pkt->senderState == this);
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pkt->setDest(origSrc);
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pkt->setDest(origSrc);
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pkt->senderState = origSenderState;
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pkt->senderState = origSenderState;
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if (partialWriteFixed)
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delete oldPkt;
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}
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}
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void partialWriteFix(Port *port)
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{
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assert(!partialWriteFixed);
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assert(expectResponse);
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int pbs = port->peerBlockSize();
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partialWriteFixed = true;
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PacketDataPtr data;
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data = new uint8_t[pbs];
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PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq,
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Packet::Broadcast, pbs);
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funcPkt->dataStatic(data);
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port->sendFunctional(funcPkt);
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assert(funcPkt->result == Packet::Success);
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delete funcPkt;
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oldPkt = pkt;
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memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr<uint8_t>(),
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pkt->getSize());
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pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq,
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Packet::Broadcast, pbs);
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pkt->dataDynamicArray(data);
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pkt->senderState = oldPkt->senderState;
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}
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void undoPartialWriteFix()
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{
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if (!partialWriteFixed)
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return;
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delete pkt;
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pkt = oldPkt;
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partialWriteFixed = false;
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}
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};
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};
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/**
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/**
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@ -140,7 +184,7 @@ class Bridge : public MemObject
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/** Constructor for the BusPort.*/
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/** Constructor for the BusPort.*/
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BridgePort(const std::string &_name,
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BridgePort(const std::string &_name,
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Bridge *_bridge, BridgePort *_otherPort,
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Bridge *_bridge, BridgePort *_otherPort,
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int _delay, int _queueLimit);
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int _delay, int _queueLimit, bool fix_partial_write);
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protected:
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protected:
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@ -182,7 +226,8 @@ class Bridge : public MemObject
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virtual void init();
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virtual void init();
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Bridge(const std::string &n, int qsa, int qsb, Tick _delay, int write_ack);
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Bridge(const std::string &n, int qsa, int qsb, Tick _delay, int write_ack,
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bool fix_partial_write_a, bool fix_partial_write_b);
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};
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};
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#endif //__MEM_BUS_HH__
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#endif //__MEM_BUS_HH__
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@ -48,6 +48,7 @@ Bus::getPort(const std::string &if_name, int idx)
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if (defaultPort == NULL) {
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if (defaultPort == NULL) {
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defaultPort = new BusPort(csprintf("%s-default",name()), this,
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defaultPort = new BusPort(csprintf("%s-default",name()), this,
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defaultId);
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defaultId);
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cachedBlockSizeValid = false;
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return defaultPort;
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return defaultPort;
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} else
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} else
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fatal("Default port already set\n");
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fatal("Default port already set\n");
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@ -68,6 +69,7 @@ Bus::getPort(const std::string &if_name, int idx)
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assert(maxId < std::numeric_limits<typeof(maxId)>::max());
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assert(maxId < std::numeric_limits<typeof(maxId)>::max());
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BusPort *bp = new BusPort(csprintf("%s-p%d", name(), id), this, id);
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BusPort *bp = new BusPort(csprintf("%s-p%d", name(), id), this, id);
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interfaces[id] = bp;
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interfaces[id] = bp;
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cachedBlockSizeValid = false;
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return bp;
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return bp;
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}
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}
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@ -182,6 +184,7 @@ Bus::recvTiming(PacketPtr pkt)
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if (tickNextIdle > curTick ||
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if (tickNextIdle > curTick ||
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(retryList.size() && (!inRetry || pktPort != retryList.front()))) {
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(retryList.size() && (!inRetry || pktPort != retryList.front()))) {
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addToRetryList(pktPort);
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addToRetryList(pktPort);
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DPRINTF(Bus, "recvTiming: Bus is busy, returning false\n");
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return false;
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return false;
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}
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}
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@ -207,11 +210,12 @@ Bus::recvTiming(PacketPtr pkt)
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inRetry = false;
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inRetry = false;
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}
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}
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occupyBus(pkt);
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occupyBus(pkt);
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DPRINTF(Bus, "recvTiming: Packet sucessfully sent\n");
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return true;
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return true;
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}
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}
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} else {
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} else {
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//Snoop didn't succeed
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//Snoop didn't succeed
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DPRINTF(Bus, "Adding a retry to RETRY list %d\n",
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DPRINTF(Bus, "Adding1 a retry to RETRY list %d\n",
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pktPort->getId());
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pktPort->getId());
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addToRetryList(pktPort);
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addToRetryList(pktPort);
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return false;
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return false;
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@ -239,13 +243,14 @@ Bus::recvTiming(PacketPtr pkt)
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}
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}
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// Packet not successfully sent. Leave or put it on the retry list.
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// Packet not successfully sent. Leave or put it on the retry list.
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DPRINTF(Bus, "Adding a retry to RETRY list %d\n",
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DPRINTF(Bus, "Adding2 a retry to RETRY list %d\n",
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pktPort->getId());
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pktPort->getId());
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addToRetryList(pktPort);
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addToRetryList(pktPort);
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return false;
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return false;
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}
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}
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else {
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else {
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//Forwarding up from responder, just return true;
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//Forwarding up from responder, just return true;
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DPRINTF(Bus, "recvTiming: can we be here?\n");
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return true;
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return true;
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}
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}
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}
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}
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@ -253,12 +258,12 @@ Bus::recvTiming(PacketPtr pkt)
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void
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void
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Bus::recvRetry(int id)
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Bus::recvRetry(int id)
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{
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{
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DPRINTF(Bus, "Received a retry\n");
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DPRINTF(Bus, "Received a retry from %s\n", id == -1 ? "self" : interfaces[id]->getPeer()->name());
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// If there's anything waiting, and the bus isn't busy...
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// If there's anything waiting, and the bus isn't busy...
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if (retryList.size() && curTick >= tickNextIdle) {
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if (retryList.size() && curTick >= tickNextIdle) {
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//retryingPort = retryList.front();
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//retryingPort = retryList.front();
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inRetry = true;
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inRetry = true;
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DPRINTF(Bus, "Sending a retry\n");
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DPRINTF(Bus, "Sending a retry to %s\n", retryList.front()->getPeer()->name());
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retryList.front()->sendRetry();
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retryList.front()->sendRetry();
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// If inRetry is still true, sendTiming wasn't called
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// If inRetry is still true, sendTiming wasn't called
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if (inRetry)
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if (inRetry)
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@ -267,18 +272,20 @@ Bus::recvRetry(int id)
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retryList.pop_front();
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retryList.pop_front();
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inRetry = false;
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inRetry = false;
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//Bring tickNextIdle up to the present
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if (id != -1) {
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while (tickNextIdle < curTick)
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//Bring tickNextIdle up to the present
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while (tickNextIdle < curTick)
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tickNextIdle += clock;
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//Burn a cycle for the missed grant.
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tickNextIdle += clock;
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tickNextIdle += clock;
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//Burn a cycle for the missed grant.
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if (!busIdle.scheduled()) {
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tickNextIdle += clock;
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busIdle.schedule(tickNextIdle);
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} else {
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if (!busIdle.scheduled()) {
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busIdle.reschedule(tickNextIdle);
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busIdle.schedule(tickNextIdle);
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}
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} else {
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} // id != -1
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busIdle.reschedule(tickNextIdle);
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}
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}
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}
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}
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}
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//If we weren't able to drain before, we might be able to now.
|
//If we weren't able to drain before, we might be able to now.
|
||||||
|
@ -598,6 +605,37 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int
|
||||||
|
Bus::findBlockSize(int id)
|
||||||
|
{
|
||||||
|
if (cachedBlockSizeValid)
|
||||||
|
return cachedBlockSize;
|
||||||
|
|
||||||
|
int max_bs = -1, tmp_bs;
|
||||||
|
range_map<Addr,int>::iterator portIter;
|
||||||
|
std::vector<DevMap>::iterator snoopIter;
|
||||||
|
for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) {
|
||||||
|
tmp_bs = interfaces[portIter->second]->peerBlockSize();
|
||||||
|
if (tmp_bs > max_bs)
|
||||||
|
max_bs = tmp_bs;
|
||||||
|
}
|
||||||
|
for (snoopIter = portSnoopList.begin();
|
||||||
|
snoopIter != portSnoopList.end(); snoopIter++) {
|
||||||
|
tmp_bs = interfaces[snoopIter->portId]->peerBlockSize();
|
||||||
|
if (tmp_bs > max_bs)
|
||||||
|
max_bs = tmp_bs;
|
||||||
|
}
|
||||||
|
if (max_bs <= 0)
|
||||||
|
max_bs = defaultBlockSize;
|
||||||
|
|
||||||
|
if (max_bs != 64)
|
||||||
|
warn_once("Blocksize found to not be 64... hmm... probably not.\n");
|
||||||
|
cachedBlockSize = max_bs;
|
||||||
|
cachedBlockSizeValid = true;
|
||||||
|
return max_bs;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
unsigned int
|
unsigned int
|
||||||
Bus::drain(Event * de)
|
Bus::drain(Event * de)
|
||||||
{
|
{
|
||||||
|
@ -618,6 +656,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
||||||
Param<int> clock;
|
Param<int> clock;
|
||||||
Param<int> width;
|
Param<int> width;
|
||||||
Param<bool> responder_set;
|
Param<bool> responder_set;
|
||||||
|
Param<int> block_size;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
||||||
|
|
||||||
|
@ -625,12 +664,14 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
|
||||||
INIT_PARAM(bus_id, "a globally unique bus id"),
|
INIT_PARAM(bus_id, "a globally unique bus id"),
|
||||||
INIT_PARAM(clock, "bus clock speed"),
|
INIT_PARAM(clock, "bus clock speed"),
|
||||||
INIT_PARAM(width, "width of the bus (bits)"),
|
INIT_PARAM(width, "width of the bus (bits)"),
|
||||||
INIT_PARAM(responder_set, "Is a default responder set by the user")
|
INIT_PARAM(responder_set, "Is a default responder set by the user"),
|
||||||
|
INIT_PARAM(block_size, "Default blocksize if no device has one")
|
||||||
END_INIT_SIM_OBJECT_PARAMS(Bus)
|
END_INIT_SIM_OBJECT_PARAMS(Bus)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(Bus)
|
CREATE_SIM_OBJECT(Bus)
|
||||||
{
|
{
|
||||||
return new Bus(getInstanceName(), bus_id, clock, width, responder_set);
|
return new Bus(getInstanceName(), bus_id, clock, width, responder_set,
|
||||||
|
block_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("Bus", Bus)
|
REGISTER_SIM_OBJECT("Bus", Bus)
|
||||||
|
|
|
@ -133,6 +133,12 @@ class Bus : public MemObject
|
||||||
/** Occupy the bus with transmitting the packet pkt */
|
/** Occupy the bus with transmitting the packet pkt */
|
||||||
void occupyBus(PacketPtr pkt);
|
void occupyBus(PacketPtr pkt);
|
||||||
|
|
||||||
|
/** Ask everyone on the bus what their size is
|
||||||
|
* @param id id of the busport that made the request
|
||||||
|
* @return the max of all the sizes
|
||||||
|
*/
|
||||||
|
int findBlockSize(int id);
|
||||||
|
|
||||||
/** Declaration of the buses port type, one will be instantiated for each
|
/** Declaration of the buses port type, one will be instantiated for each
|
||||||
of the interfaces connecting to the bus. */
|
of the interfaces connecting to the bus. */
|
||||||
class BusPort : public Port
|
class BusPort : public Port
|
||||||
|
@ -195,8 +201,11 @@ class Bus : public MemObject
|
||||||
AddrRangeList &snoop)
|
AddrRangeList &snoop)
|
||||||
{ bus->addressRanges(resp, snoop, id); }
|
{ bus->addressRanges(resp, snoop, id); }
|
||||||
|
|
||||||
// Hack to make translating port work without changes
|
// Ask the bus to ask everyone on the bus what their block size is and
|
||||||
virtual int deviceBlockSize() { return 32; }
|
// take the max of it. This might need to be changed a bit if we ever
|
||||||
|
// support multiple block sizes.
|
||||||
|
virtual int deviceBlockSize()
|
||||||
|
{ return bus->findBlockSize(id); }
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -256,6 +265,10 @@ class Bus : public MemObject
|
||||||
/** Has the user specified their own default responder? */
|
/** Has the user specified their own default responder? */
|
||||||
bool responderSet;
|
bool responderSet;
|
||||||
|
|
||||||
|
int defaultBlockSize;
|
||||||
|
int cachedBlockSize;
|
||||||
|
bool cachedBlockSizeValid;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
/** A function used to return the port associated with this bus object. */
|
/** A function used to return the port associated with this bus object. */
|
||||||
|
@ -267,11 +280,12 @@ class Bus : public MemObject
|
||||||
unsigned int drain(Event *de);
|
unsigned int drain(Event *de);
|
||||||
|
|
||||||
Bus(const std::string &n, int bus_id, int _clock, int _width,
|
Bus(const std::string &n, int bus_id, int _clock, int _width,
|
||||||
bool responder_set)
|
bool responder_set, int dflt_blk_size)
|
||||||
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
|
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
|
||||||
tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
|
tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
|
||||||
maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
|
maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
|
||||||
responderSet(responder_set)
|
responderSet(responder_set), defaultBlockSize(dflt_blk_size),
|
||||||
|
cachedBlockSize(0), cachedBlockSizeValid(false)
|
||||||
{
|
{
|
||||||
//Both the width and clock period must be positive
|
//Both the width and clock period must be positive
|
||||||
if (width <= 0)
|
if (width <= 0)
|
||||||
|
|
|
@ -85,7 +85,7 @@ MemCmd::commandInfo[] =
|
||||||
{ SET5(IsWrite, IsInvalidate, IsRequest, HasData, NeedsResponse),
|
{ SET5(IsWrite, IsInvalidate, IsRequest, HasData, NeedsResponse),
|
||||||
WriteInvalidateResp, "WriteInvalidateReq" },
|
WriteInvalidateResp, "WriteInvalidateReq" },
|
||||||
/* WriteInvalidateResp */
|
/* WriteInvalidateResp */
|
||||||
{ SET5(IsWrite, IsInvalidate, IsRequest, NeedsResponse, IsResponse),
|
{ SET3(IsWrite, IsInvalidate, IsResponse),
|
||||||
InvalidCmd, "WriteInvalidateResp" },
|
InvalidCmd, "WriteInvalidateResp" },
|
||||||
/* UpgradeReq */
|
/* UpgradeReq */
|
||||||
{ SET3(IsInvalidate, IsRequest, IsUpgrade), InvalidCmd, "UpgradeReq" },
|
{ SET3(IsInvalidate, IsRequest, IsUpgrade), InvalidCmd, "UpgradeReq" },
|
||||||
|
|
|
@ -161,10 +161,10 @@ class Port
|
||||||
|
|
||||||
/** Called by a peer port in order to determine the block size of the
|
/** Called by a peer port in order to determine the block size of the
|
||||||
device connected to this port. It sometimes doesn't make sense for
|
device connected to this port. It sometimes doesn't make sense for
|
||||||
this function to be called, a DMA interface doesn't really have a
|
this function to be called, so it just returns 0. Anytthing that is
|
||||||
block size, so it is defaulted to a panic.
|
concerned with the size should just ignore that.
|
||||||
*/
|
*/
|
||||||
virtual int deviceBlockSize() { panic("??"); M5_DUMMY_RETURN }
|
virtual int deviceBlockSize() { return 0; }
|
||||||
|
|
||||||
/** The peer port is requesting us to reply with a list of the ranges we
|
/** The peer port is requesting us to reply with a list of the ranges we
|
||||||
are responsible for.
|
are responsible for.
|
||||||
|
|
|
@ -9,3 +9,5 @@ class Bridge(MemObject):
|
||||||
queue_size_b = Param.Int(16, "The number of requests to buffer")
|
queue_size_b = Param.Int(16, "The number of requests to buffer")
|
||||||
delay = Param.Latency('0ns', "The latency of this bridge")
|
delay = Param.Latency('0ns', "The latency of this bridge")
|
||||||
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
||||||
|
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
|
||||||
|
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
|
||||||
|
|
|
@ -11,6 +11,7 @@ class Bus(MemObject):
|
||||||
clock = Param.Clock("1GHz", "bus clock speed")
|
clock = Param.Clock("1GHz", "bus clock speed")
|
||||||
width = Param.Int(64, "bus width (bytes)")
|
width = Param.Int(64, "bus width (bytes)")
|
||||||
responder_set = Param.Bool(False, "Did the user specify a default responder.")
|
responder_set = Param.Bool(False, "Did the user specify a default responder.")
|
||||||
|
block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
|
||||||
if build_env['FULL_SYSTEM']:
|
if build_env['FULL_SYSTEM']:
|
||||||
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
|
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
|
||||||
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
|
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
|
||||||
|
|
Loading…
Reference in a new issue