Registers: Eliminate the ISA defined floating point register file.

src/arch/alpha/SConscript

@@ -34,7 +34,6 @@ Import('*')
 if env['TARGET_ISA'] == 'alpha':
     Source('ev5.cc')
     Source('faults.cc')
-    Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('ipr.cc')
     Source('isa.cc')

src/arch/alpha/floatregfile.cc

@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- *          Kevin Lim
- */
-
-#include <cstring>
-
-#include "arch/alpha/floatregfile.hh"
-#include "sim/serialize.hh"
-
-namespace AlphaISA {
-void
-FloatRegFile::clear()
-{
-    std::memset(d, 0, sizeof(d));
-}
-
-void
-FloatRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(q, NumFloatRegs);
-}
-
-void
-FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(q, NumFloatRegs);
-}
-
-} // namespace AlphaISA

src/arch/alpha/floatregfile.hh

@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_FLOATREGFILE_HH__
-#define __ARCH_ALPHA_FLOATREGFILE_HH__
-
-#include <iosfwd>
-#include <string>
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/types.hh"
-
-class Checkpoint;
-
-namespace AlphaISA {
-
-class FloatRegFile
-{
-  public:
-    union {
-        uint64_t q[NumFloatRegs];   // integer qword view
-        double d[NumFloatRegs];     // double-precision floating point view
-    };
-
-    void clear();
-
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
-
-    FloatReg
-    readReg(int floatReg)
-    {
-        return d[floatReg];
-    }
-
-    FloatRegBits
-    readRegBits(int floatReg)
-    {
-        return q[floatReg];
-    }
-
-    void
-    setReg(int floatReg, const FloatReg &val)
-    {
-        d[floatReg] = val;
-    }
-
-    void
-    setRegBits(int floatReg, const FloatRegBits &val)
-    {
-        q[floatReg] = val;
-    }
-
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_FLOATREGFILE_HH__

src/arch/alpha/regfile.cc

@@ -42,7 +42,6 @@ void
 RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
-    floatRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
@@ -54,7 +53,6 @@ void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM

src/arch/alpha/regfile.hh

@@ -32,7 +32,6 @@
 #define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/floatregfile.hh"
 #include "arch/alpha/intregfile.hh"
 #include "arch/alpha/miscregfile.hh"
 #include "arch/alpha/types.hh"
@@ -92,7 +91,6 @@ class RegFile {
 
   protected:
     IntRegFile intRegFile;          // (signed) integer register file
-    FloatRegFile floatRegFile;      // floating point register file
 
   public:
 #if FULL_SYSTEM
@@ -103,31 +101,6 @@ class RegFile {
     clear()
     {
         intRegFile.clear();
-        floatRegFile.clear();
-    }
-
-    FloatReg
-    readFloatReg(int floatReg)
-    {
-        return floatRegFile.d[floatReg];
-    }
-
-    FloatRegBits
-    readFloatRegBits(int floatReg)
-    {
-        return floatRegFile.q[floatReg];
-    }
-
-    void
-    setFloatReg(int floatReg, const FloatReg &val)
-    {
-        floatRegFile.d[floatReg] = val;
-    }
-
-    void
-    setFloatRegBits(int floatReg, const FloatRegBits &val)
-    {
-        floatRegFile.q[floatReg] = val;
     }
 
     IntReg

src/arch/arm/regfile/float_regfile.hh

@@ -1,140 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__
-
-#include "arch/arm/types.hh"
-#include "arch/arm/isa_traits.hh"
-#include "base/misc.hh"
-#include "base/bitfield.hh"
-#include "sim/faults.hh"
-#include "sim/serialize.hh"
-
-#include <string>
-
-class Checkpoint;
-
-namespace ArmISA
-{
-    static inline std::string getFloatRegName(RegIndex)
-    {
-        return "";
-    }
-
-    const uint32_t ARM32_QNAN = 0x7fbfffff;
-    const uint64_t ARM64_QNAN = ULL(0x7fbfffffffffffff);
-
-    enum FPControlRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
-    enum FCSRBits {
-        Inexact = 1,
-        Underflow,
-        Overflow,
-        DivideByZero,
-        Invalid,
-        Unimplemented
-    };
-
-    enum FCSRFields {
-        Flag_Field = 1,
-        Enable_Field = 6,
-        Cause_Field = 11
-    };
-
-    class FloatRegFile
-    {
-      protected:
-          union {
-            FloatRegBits qregs[NumFloatRegs];
-            FloatReg regs[NumFloatRegs];
-          };
-
-      public:
-
-        void clear()
-        {
-            bzero(regs, sizeof(regs));
-            regs[8] = 0.0;
-            regs[9] = 1.0;
-            regs[10] = 2.0;
-            regs[11] = 3.0;
-            regs[12] = 4.0;
-            regs[13] = 5.0;
-            regs[14] = 0.5;
-            regs[15] = 10.0;
-        }
-
-        FloatReg readReg(int floatReg)
-        {
-            return regs[floatReg];
-        }
-
-        FloatRegBits readRegBits(int floatReg)
-        {
-            return qregs[floatReg];
-        }
-
-        Fault setReg(int floatReg, const FloatReg &val)
-        {
-            if (floatReg > 7)
-                panic("Writing to a hard-wired FP register");
-            regs[floatReg] = val;
-            return NoFault;
-        }
-
-        Fault setRegBits(int floatReg, const FloatRegBits &val)
-        {
-            if (floatReg > 7)
-                panic("Writing to a hard-wired FP register");
-            qregs[floatReg] = val;
-            return NoFault;
-        }
-
-        void serialize(std::ostream &os)
-        {
-            SERIALIZE_ARRAY(regs, NumFloatRegs);
-        }
-
-        void unserialize(Checkpoint *cp, const std::string &section)
-        {
-            UNSERIALIZE_ARRAY(regs, NumFloatRegs);
-        }
-    };
-
-} // namespace ArmISA
-
-#endif

src/arch/arm/regfile/regfile.cc

@@ -58,7 +58,6 @@ void
 RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
-    //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
 }
@@ -67,7 +66,6 @@ void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
-    //UNSERIALIZE_ARRAY(floatRegFile);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
 }

src/arch/arm/regfile/regfile.hh

@@ -33,7 +33,6 @@
 
 #include "arch/arm/types.hh"
 #include "arch/arm/regfile/int_regfile.hh"
-#include "arch/arm/regfile/float_regfile.hh"
 #include "arch/arm/regfile/misc_regfile.hh"
 #include "sim/faults.hh"
 
@@ -43,38 +42,39 @@ class ThreadContext;
 
 namespace ArmISA
 {
+    enum FPControlRegNums {
+       FIR = NumFloatArchRegs,
+       FCCR,
+       FEXR,
+       FENR,
+       FCSR
+    };
+
+    enum FCSRBits {
+        Inexact = 1,
+        Underflow,
+        Overflow,
+        DivideByZero,
+        Invalid,
+        Unimplemented
+    };
+
+    enum FCSRFields {
+        Flag_Field = 1,
+        Enable_Field = 6,
+        Cause_Field = 11
+    };
+
     class RegFile
     {
       protected:
         IntRegFile intRegFile;		// (signed) integer register file
-        FloatRegFile floatRegFile;	// floating point register file
 
       public:
 
         void clear()
         {
             intRegFile.clear();
-            floatRegFile.clear();
-        }
-
-        FloatReg readFloatReg(int floatReg)
-        {
-            return floatRegFile.readReg(floatReg);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg)
-        {
-            return floatRegFile.readRegBits(floatReg);
-        }
-
-        void setFloatReg(int floatReg, const FloatReg &val)
-        {
-            floatRegFile.setReg(floatReg, val);
-        }
-
-        void setFloatRegBits(int floatReg, const FloatRegBits &val)
-        {
-            floatRegFile.setRegBits(floatReg, val);
         }
 
         IntReg readIntReg(int intReg)

src/arch/mips/SConscript

@@ -36,7 +36,6 @@ if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
     Source('isa.cc')
     Source('regfile/int_regfile.cc')
-    Source('regfile/float_regfile.cc')
     Source('regfile/misc_regfile.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')

src/arch/mips/regfile.cc

@@ -38,7 +38,6 @@
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
-#include "arch/mips/regfile/float_regfile.hh"
 #include "arch/mips/regfile/misc_regfile.hh"
 #include "sim/faults.hh"
 
@@ -50,7 +49,6 @@ using namespace MipsISA;
 void RegFile::clear()
 {
     intRegFile.clear();
-    floatRegFile.clear();
     miscRegFile.clear();
 }
 
@@ -59,7 +57,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads,
                unsigned num_vpes)
 {
     bzero(&intRegFile, sizeof(intRegFile));
-    bzero(&floatRegFile, sizeof(floatRegFile));
     miscRegFile.reset(core_name, num_threads, num_vpes);
 }
 
@@ -98,26 +95,6 @@ RegFile::setMiscReg(int miscReg, const MiscReg &val,
     miscRegFile.setReg(miscReg, val, tc, tid);
 }
 
-FloatRegVal RegFile::readFloatReg(int floatReg)
-{
-    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg)
-{
-    return floatRegFile.readRegBits(floatReg);
-}
-
-Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
-{
-    return floatRegFile.setReg(floatReg, val);
-}
-
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
-{
-    return floatRegFile.setRegBits(floatReg, val);
-}
-
 Addr RegFile::readPC()
 {
     return pc;
@@ -152,7 +129,6 @@ void
 RegFile::serialize(std::ostream &os)
 {
     intRegFile.serialize(os);
-    floatRegFile.serialize(os);
     miscRegFile.serialize(os);
 
     SERIALIZE_SCALAR(pc);
@@ -165,7 +141,6 @@ void
 RegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
     intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
     miscRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);

src/arch/mips/regfile/float_regfile.cc

@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Korey Sewell
- */
-
-#include "arch/mips/regfile/float_regfile.hh"
-#include "sim/serialize.hh"
-
-using namespace MipsISA;
-using namespace std;
-
-void
-FloatRegFile::clear()
-{
-    bzero(regs.q, sizeof(regs.q));
-}
-
-FloatReg
-FloatRegFile::readReg(int floatReg)
-{
-    return regs.s[floatReg];
-}
-
-FloatRegBits
-FloatRegFile::readRegBits(int floatReg)
-{
-    return regs.q[floatReg];
-}
-
-Fault
-FloatRegFile::setReg(int floatReg, const FloatReg &val)
-{
-    regs.s[floatReg] = val;
-    return NoFault;
-}
-
-Fault
-FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
-{
-    regs.q[floatReg] = val;
-    return NoFault;
-}
-
-void
-FloatRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs.q, NumFloatRegs);
-}
-
-void
-FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs.q, NumFloatRegs);
-}

src/arch/mips/regfile/float_regfile.hh

@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
-#define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
-
-#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
-#include "base/misc.hh"
-#include "base/bitfield.hh"
-#include "sim/faults.hh"
-
-#include <string>
-
-class Checkpoint;
-
-namespace MipsISA
-{
-    const uint32_t MIPS32_QNAN = 0x7fbfffff;
-    const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
-
-    enum FPControlRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
-    enum FCSRBits {
-        Inexact = 1,
-        Underflow,
-        Overflow,
-        DivideByZero,
-        Invalid,
-        Unimplemented
-    };
-
-    enum FCSRFields {
-        Flag_Field = 1,
-        Enable_Field = 6,
-        Cause_Field = 11
-    };
-
-    class FloatRegFile
-    {
-      protected:
-        union {
-            FloatReg s[NumFloatRegs];
-            FloatRegBits q[NumFloatRegs];
-        } regs;
-
-      public:
-        void clear();
-        FloatReg readReg(int floatReg);
-        FloatRegBits readRegBits(int floatReg);
-        Fault setReg(int floatReg, const FloatReg &val);
-        Fault setRegBits(int floatReg, const FloatRegBits &val);
-
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-} // namespace MipsISA
-
-#endif

src/arch/mips/regfile/regfile.cc

@@ -41,7 +41,6 @@ void
 RegFile::clear()
 {
     intRegFile.clear();
-    floatRegFile.clear();
 }
 
 void
@@ -49,7 +48,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
                BaseCPU *_cpu)
 {
     bzero(&intRegFile, sizeof(intRegFile));
-    bzero(&floatRegFile, sizeof(floatRegFile));
 }
 
 IntReg
@@ -64,30 +62,6 @@ RegFile::setIntReg(int intReg, const IntReg &val)
     return intRegFile.setReg(intReg, val);
 }
 
-FloatReg
-RegFile::readFloatReg(int floatReg)
-{
-    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegBits
-RegFile::readFloatRegBits(int floatReg)
-{
-    return floatRegFile.readRegBits(floatReg);
-}
-
-Fault
-RegFile::setFloatReg(int floatReg, const FloatReg &val)
-{
-    return floatRegFile.setReg(floatReg, val);
-}
-
-Fault
-RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
-{
-    return floatRegFile.setRegBits(floatReg, val);
-}
-
 void
 RegFile::setShadowSet(int css){
     intRegFile.setShadowSet(css);
@@ -134,7 +108,6 @@ void
 RegFile::serialize(EventManager *em, std::ostream &os)
 {
     intRegFile.serialize(os);
-    //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -145,7 +118,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp,
     const std::string &section)
 {
     intRegFile.unserialize(cp, section);
-    //UNSERIALIZE_ARRAY(floatRegFile);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);

src/arch/mips/regfile/regfile.hh

@@ -36,7 +36,6 @@
 #include "arch/mips/isa_traits.hh"
 //#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
-#include "arch/mips/regfile/float_regfile.hh"
 //#include "cpu/base.hh"
 #include "sim/faults.hh"
 
@@ -46,6 +45,32 @@ class EventManager;
 
 namespace MipsISA
 {
+    const uint32_t MIPS32_QNAN = 0x7fbfffff;
+    const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
+
+    enum FPControlRegNums {
+       FIR = NumFloatArchRegs,
+       FCCR,
+       FEXR,
+       FENR,
+       FCSR
+    };
+
+    enum FCSRBits {
+        Inexact = 1,
+        Underflow,
+        Overflow,
+        DivideByZero,
+        Invalid,
+        Unimplemented
+    };
+
+    enum FCSRFields {
+        Flag_Field = 1,
+        Enable_Field = 6,
+        Cause_Field = 11
+    };
+
     class RegFile {
       protected:
         Addr pc;                        // program counter
@@ -55,7 +80,6 @@ namespace MipsISA
                                         // not real register
 
         IntRegFile intRegFile;          // (signed) integer register file
-        FloatRegFile floatRegFile;      // floating point register file
 
       public:
         void clear();
@@ -65,13 +89,6 @@ namespace MipsISA
         IntReg readIntReg(int intReg);
         Fault setIntReg(int intReg, const IntReg &val);
 
-
-        FloatReg readFloatReg(int floatReg);
-        FloatRegBits readFloatRegBits(int floatReg);
-        Fault setFloatReg(int floatReg, const FloatReg &val);
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
-
-
         void setShadowSet(int css);
 
       public:

src/arch/sparc/SConscript

@@ -34,7 +34,6 @@ Import('*')
 if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
-    Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('isa.cc')
     Source('miscregfile.cc')

src/arch/sparc/floatregfile.cc

@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#include "arch/sparc/floatregfile.hh"
-#include "base/trace.hh"
-#include "sim/byteswap.hh"
-#include "sim/serialize.hh"
-
-#include <string.h>
-
-using namespace SparcISA;
-using namespace std;
-
-class Checkpoint;
-
-void FloatRegFile::clear()
-{
-    memset(regs.q, 0, sizeof(regs.q));
-}
-
-FloatReg FloatRegFile::readReg(int floatReg)
-{
-    return regs.s[floatReg];
-}
-
-FloatRegBits FloatRegFile::readRegBits(int floatReg)
-{
-    return regs.q[floatReg];
-}
-
-Fault FloatRegFile::setReg(int floatReg, const FloatReg &val)
-{
-    regs.s[floatReg] = val;
-    return NoFault;
-}
-
-Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
-{
-    regs.q[floatReg] = val;
-    return NoFault;
-}
-
-void FloatRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs.q, NumFloatRegs);
-}
-
-void FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs.q, NumFloatRegs);
-}
-

src/arch/sparc/floatregfile.hh

@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#ifndef __ARCH_SPARC_FLOATREGFILE_HH__
-#define __ARCH_SPARC_FLOATREGFILE_HH__
-
-#include "arch/sparc/faults.hh"
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/types.hh"
-
-#include <string>
-
-class Checkpoint;
-
-namespace SparcISA
-{
-    const int NumFloatArchRegs = 64;
-    const int NumFloatRegs = 64;
-
-    class FloatRegFile
-    {
-      protected:
-        union {
-            uint32_t q[NumFloatRegs];
-            float s[NumFloatRegs];
-        } regs;
-
-      public:
-
-        void clear();
-
-        FloatReg readReg(int floatReg);
-
-        FloatRegBits readRegBits(int floatReg);
-
-        Fault setReg(int floatReg, const FloatReg &val);
-
-        Fault setRegBits(int floatReg, const FloatRegBits &val);
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-}
-
-#endif

src/arch/sparc/regfile.cc

@@ -70,30 +70,9 @@ void RegFile::setNextNPC(Addr val)
 
 void RegFile::clear()
 {
-    floatRegFile.clear();
     intRegFile.clear();
 }
 
-FloatReg RegFile::readFloatReg(int floatReg)
-{
-    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg)
-{
-    return floatRegFile.readRegBits(floatReg);
-}
-
-void RegFile::setFloatReg(int floatReg, const FloatReg &val)
-{
-    floatRegFile.setReg(floatReg, val);
-}
-
-void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
-{
-    floatRegFile.setRegBits(floatReg, val);
-}
-
 IntReg RegFile::readIntReg(int intReg)
 {
     return intRegFile.readReg(intReg);
@@ -108,7 +87,6 @@ void
 RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
-    floatRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -118,7 +96,6 @@ void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);

src/arch/sparc/regfile.hh

@@ -34,7 +34,6 @@
 
 #include <string>
 
-#include "arch/sparc/floatregfile.hh"
 #include "arch/sparc/intregfile.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/miscregfile.hh"
@@ -64,20 +63,11 @@ namespace SparcISA
 
       protected:
         IntRegFile intRegFile;          // integer register file
-        FloatRegFile floatRegFile;      // floating point register file
 
       public:
 
         void clear();
 
-        FloatReg readFloatReg(int floatReg);
-
-        FloatRegBits readFloatRegBits(int floatReg);
-
-        void setFloatReg(int floatReg, const FloatReg &val);
-
-        void setFloatRegBits(int floatReg, const FloatRegBits &val);
-
         IntReg readIntReg(int intReg);
 
         void setIntReg(int intReg, const IntReg &val);

src/arch/sparc/sparc_traits.hh

@@ -49,7 +49,8 @@ namespace SparcISA
 //    const int NumIntRegs =
 //      NumRegularIntRegs +
 //      NumMicroIntRegs;
-//    const int NumFloatRegs = 64;
+    const int NumFloatRegs = 64;
+    const int NumFloatArchRegs = NumFloatRegs;
 //    const int NumMiscRegs = 40;
 }
 

src/arch/x86/SConscript

@@ -88,7 +88,6 @@ Import('*')
 if env['TARGET_ISA'] == 'x86':
     Source('cpuid.cc')
     Source('emulenv.cc')
-    Source('floatregfile.cc')
     Source('faults.cc')
     Source('insts/microfpop.cc')
     Source('insts/microldstop.cc')

src/arch/x86/floatregfile.cc

@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2003-2007 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
- *
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use.  Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- *     Director of Intellectual Property Licensing
- *     Office of Strategy and Technology
- *     Hewlett-Packard Company
- *     1501 Page Mill Road
- *     Palo Alto, California  94304
- *
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.  Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.  Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.  No right of
- * sublicense is granted herewith.  Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses.  Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/x86/floatregfile.hh"
-#include "base/trace.hh"
-#include "sim/serialize.hh"
-
-#include <string.h>
-
-using namespace X86ISA;
-using namespace std;
-
-class Checkpoint;
-
-void FloatRegFile::clear()
-{
-    memset(q, 0, sizeof(FloatReg) * NumFloatRegs);
-}
-
-FloatReg FloatRegFile::readReg(int floatReg)
-{
-    FloatReg reg = d[floatReg];
-    DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg);
-    return reg;
-}
-
-FloatRegBits FloatRegFile::readRegBits(int floatReg)
-{
-    FloatRegBits reg = q[floatReg];
-    DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg);
-    return reg;
-}
-
-Fault FloatRegFile::setReg(int floatReg, const FloatReg &val)
-{
-    DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg);
-    d[floatReg] = val;
-    return NoFault;
-}
-
-Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
-{
-    DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg);
-    q[floatReg] = val;
-    return NoFault;
-}
-
-void FloatRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(q, NumFloatRegs);
-}
-
-void FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(q, NumFloatRegs);
-}
-

src/arch/x86/floatregfile.hh

@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2003-2007 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
- *
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use.  Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- *     Director of Intellectual Property Licensing
- *     Office of Strategy and Technology
- *     Hewlett-Packard Company
- *     1501 Page Mill Road
- *     Palo Alto, California  94304
- *
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.  Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.  Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.  No right of
- * sublicense is granted herewith.  Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses.  Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_X86_FLOATREGFILE_HH__
-#define __ARCH_X86_FLOATREGFILE_HH__
-
-#include <string>
-
-#include "arch/x86/faults.hh"
-#include "arch/x86/types.hh"
-#include "arch/x86/x86_traits.hh"
-
-class Checkpoint;
-
-namespace X86ISA
-{
-    //Each 128 bit xmm register is broken into two effective 64 bit registers.
-    const int NumFloatRegs =
-        NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
-    const int NumFloatArchRegs = NumFloatRegs + 8;
-
-    class FloatRegFile
-    {
-      protected:
-        union
-        {
-            uint64_t q[NumFloatRegs];
-            double d[NumFloatRegs];
-        };
-
-      public:
-        void clear();
-
-        FloatReg readReg(int floatReg);
-
-        FloatRegBits readRegBits(int floatReg);
-
-        Fault setReg(int floatReg, const FloatReg &val);
-
-        Fault setRegBits(int floatReg, const FloatRegBits &val);
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-}
-
-#endif //__ARCH_X86_FLOATREGFILE_HH__

src/arch/x86/regfile.cc

@@ -129,30 +129,9 @@ void RegFile::setNextNPC(Addr val)
 
 void RegFile::clear()
 {
-    floatRegFile.clear();
     intRegFile.clear();
 }
 
-FloatReg RegFile::readFloatReg(int floatReg)
-{
-    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg)
-{
-    return floatRegFile.readRegBits(floatReg);
-}
-
-void RegFile::setFloatReg(int floatReg, const FloatReg &val)
-{
-    floatRegFile.setReg(floatReg, val);
-}
-
-void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
-{
-    floatRegFile.setRegBits(floatReg, val);
-}
-
 IntReg RegFile::readIntReg(int intReg)
 {
     return intRegFile.readReg(intReg);
@@ -193,12 +172,10 @@ void
 RegFile::serialize(EventManager *em, std::ostream &os)
 {
     intRegFile.serialize(os);
-    floatRegFile.serialize(os);
 }
 
 void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
 }

src/arch/x86/regfile.hh

@@ -60,21 +60,27 @@
 
 #include <string>
 
-#include "arch/x86/floatregfile.hh"
 #include "arch/x86/intregfile.hh"
 #include "arch/x86/miscregs.hh"
 #include "arch/x86/isa_traits.hh"
+#include "arch/x86/x86_traits.hh"
 #include "arch/x86/types.hh"
 #include "base/types.hh"
 
 class Checkpoint;
 class EventManager;
+class ThreadContext;
 
 namespace X86ISA
 {
     const int NumMiscArchRegs = NUM_MISCREGS;
     const int NumMiscRegs = NUM_MISCREGS;
 
+    //Each 128 bit xmm register is broken into two effective 64 bit registers.
+    const int NumFloatRegs =
+        NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
+    const int NumFloatArchRegs = NumFloatRegs + 8;
+
     class RegFile
     {
       protected:
@@ -93,20 +99,11 @@ namespace X86ISA
 
       protected:
         IntRegFile intRegFile; // integer register file
-        FloatRegFile floatRegFile; // floating point register file
 
       public:
 
         void clear();
 
-        FloatReg readFloatReg(int floatReg);
-
-        FloatRegBits readFloatRegBits(int floatReg);
-
-        void setFloatReg(int floatReg, const FloatReg &val);
-
-        void setFloatRegBits(int floatReg, const FloatRegBits &val);
-
         IntReg readIntReg(int intReg);
 
         void setIntReg(int intReg, const IntReg &val);

src/arch/x86/tlb.cc

@@ -59,6 +59,7 @@
 
 #include "config/full_system.hh"
 
+#include "arch/x86/faults.hh"
 #include "arch/x86/insts/microldstop.hh"
 #include "arch/x86/miscregs.hh"
 #include "arch/x86/pagetable.hh"

src/cpu/inorder/cpu.cc

@@ -265,7 +265,7 @@ InOrderCPU::InOrderCPU(Params *params)
         lastSquashCycle[tid] = 0;
 
         intRegFile[tid].clear();
-        floatRegFile[tid].clear();
+        memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
         isa[tid].clear();
 
         isa[tid].expandForMultithreading(numThreads, numVirtProcs);
@@ -892,13 +892,13 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 FloatReg
 InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 {
-    return floatRegFile[tid].readReg(reg_idx);
+    return floatRegs.f[tid][reg_idx];
 }
 
 FloatRegBits
 InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 {;
-    return floatRegFile[tid].readRegBits(reg_idx);
+    return floatRegs.i[tid][reg_idx];
 }
 
 void
@@ -911,14 +911,14 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 void
 InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
 {
-    floatRegFile[tid].setReg(reg_idx, val);
+    floatRegs.f[tid][reg_idx] = val;
 }
 
 
 void
 InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
 {
-    floatRegFile[tid].setRegBits(reg_idx, val);
+    floatRegs.i[tid][reg_idx] = val;
 }
 
 uint64_t

src/cpu/inorder/cpu.hh

@@ -259,7 +259,10 @@ class InOrderCPU : public BaseCPU
 
     /** The Register File for the CPU */
     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
-    TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
+    union {
+        FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
+        FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
+    } floatRegs;
 
     /** ISA state */
     TheISA::ISA isa[ThePipeline::MaxThreads];

src/cpu/simple_thread.cc

@@ -192,6 +192,7 @@ SimpleThread::serialize(ostream &os)
 {
     ThreadState::serialize(os);
     regs.serialize(cpu, os);
+    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 
@@ -201,6 +202,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
 {
     ThreadState::unserialize(cp, section);
     regs.unserialize(cpu, cp, section);
+    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 

src/cpu/simple_thread.hh

@@ -99,6 +99,10 @@ class SimpleThread : public ThreadState
 
   protected:
     RegFile regs;       // correct-path register context
+    union {
+        FloatReg f[TheISA::NumFloatRegs];
+        FloatRegBits i[TheISA::NumFloatRegs];
+    } floatRegs;
     TheISA::ISA isa;    // one "instance" of the current ISA.
 
   public:
@@ -223,7 +227,11 @@ class SimpleThread : public ThreadState
 
     void copyArchRegs(ThreadContext *tc);
 
-    void clearArchRegs() { regs.clear(); }
+    void clearArchRegs()
+    {
+        regs.clear();
+        memset(floatRegs.i, 0, sizeof(floatRegs.i));
+    }
 
     //
     // New accessors for new decoder.
@@ -237,13 +245,13 @@ class SimpleThread : public ThreadState
     FloatReg readFloatReg(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatReg(flatIndex);
+        return floatRegs.f[flatIndex];
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatRegBits(flatIndex);
+        return floatRegs.i[flatIndex];
     }
 
     void setIntReg(int reg_idx, uint64_t val)
@@ -255,13 +263,13 @@ class SimpleThread : public ThreadState
     void setFloatReg(int reg_idx, FloatReg val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatReg(flatIndex, val);
+        floatRegs.f[flatIndex] = val;
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatRegBits(flatIndex, val);
+        floatRegs.i[flatIndex] = val;
     }
 
     uint64_t readPC()