mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv
A response to a ReadReq can either be a ReadResp or a ReadRespWithInvalidate. As we add targets to an MSHR for a ReadReq we assume that the response will be a ReadResp. When the response is invalidating (ReadRespWithInvalidate) servicing more than one targets can potentially violate the memory ordering. This change fixes the way we handle a ReadRespWithInvalidate. When a cache receives a ReadRespWithInvalidate we service only the first FromCPU target and all the FromSnoop targets from the MSHR target list. The rest of the FromCPU targets are deferred and serviced by a new request. Change-Id: I75c30c268851987ee5f8644acb46f440b4eeeec2 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
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3 changed files with 83 additions and 19 deletions
18
src/mem/cache/cache.cc
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18
src/mem/cache/cache.cc
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@ -1330,12 +1330,10 @@ Cache::recvTimingResp(PacketPtr pkt)
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int initial_offset = initial_tgt->pkt->getOffset(blkSize);
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bool from_cache = false;
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while (mshr->hasTargets()) {
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MSHR::Target *target = mshr->getTarget();
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Packet *tgt_pkt = target->pkt;
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switch (target->source) {
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MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
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for (auto &target: targets) {
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Packet *tgt_pkt = target.pkt;
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switch (target.source) {
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case MSHR::Target::FromCPU:
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Tick completion_time;
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// Here we charge on completion_time the delay of the xbar if the
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@ -1370,7 +1368,7 @@ Cache::recvTimingResp(PacketPtr pkt)
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mshr->promoteWritable();
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// NB: we use the original packet here and not the response!
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blk = handleFill(tgt_pkt, blk, writebacks,
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mshr->allocOnFill());
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targets.allocOnFill);
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assert(blk != nullptr);
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// treat as a fill, and discard the invalidation
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@ -1400,7 +1398,7 @@ Cache::recvTimingResp(PacketPtr pkt)
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assert(tgt_pkt->req->masterId() < system->maxMasters());
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missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
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completion_time - target->recvTime;
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completion_time - target.recvTime;
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} else if (pkt->cmd == MemCmd::UpgradeFailResp) {
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// failed StoreCond upgrade
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assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
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@ -1462,10 +1460,8 @@ Cache::recvTimingResp(PacketPtr pkt)
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break;
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default:
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panic("Illegal target->source enum %d\n", target->source);
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panic("Illegal target->source enum %d\n", target.source);
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}
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mshr->popTarget();
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}
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maintainClusivity(from_cache, blk);
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42
src/mem/cache/mshr.cc
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42
src/mem/cache/mshr.cc
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@ -190,6 +190,7 @@ MSHR::TargetList::clearDownstreamPending()
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if (mshr != nullptr) {
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mshr->clearDownstreamPending();
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}
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t.markedPending = false;
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}
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}
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}
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@ -455,17 +456,54 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
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return true;
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}
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MSHR::TargetList
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MSHR::extractServiceableTargets(PacketPtr pkt)
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{
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TargetList ready_targets;
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// If the downstream MSHR got an invalidation request then we only
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// service the first of the FromCPU targets and any other
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// non-FromCPU target. This way the remaining FromCPU targets
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// issue a new request and get a fresh copy of the block and we
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// avoid memory consistency violations.
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if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
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auto it = targets.begin();
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assert(it->source == Target::FromCPU);
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ready_targets.push_back(*it);
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it = targets.erase(it);
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while (it != targets.end()) {
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if (it->source == Target::FromCPU) {
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it++;
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} else {
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assert(it->source == Target::FromSnoop);
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ready_targets.push_back(*it);
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it = targets.erase(it);
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}
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}
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ready_targets.populateFlags();
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} else {
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std::swap(ready_targets, targets);
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}
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targets.populateFlags();
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return ready_targets;
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}
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bool
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MSHR::promoteDeferredTargets()
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{
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assert(targets.empty());
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if (targets.empty()) {
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if (deferredTargets.empty()) {
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return false;
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}
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// swap targets & deferredTargets lists
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std::swap(targets, deferredTargets);
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} else {
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// If the targets list is not empty then we have one targets
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// from the deferredTargets list to the targets list. A new
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// request will then service the targets list.
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targets.splice(targets.end(), deferredTargets);
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targets.populateFlags();
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}
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// clear deferredTargets flags
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deferredTargets.resetFlags();
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34
src/mem/cache/mshr.hh
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34
src/mem/cache/mshr.hh
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@ -126,8 +126,24 @@ class MSHR : public QueueEntry, public Printable
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const Counter order; //!< Global order (for memory consistency mgmt)
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const PacketPtr pkt; //!< Pending request packet.
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const Source source; //!< Request from cpu, memory, or prefetcher?
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const bool markedPending; //!< Did we mark upstream MSHR
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//!< as downstreamPending?
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/**
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* We use this flag to track whether we have cleared the
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* downstreamPending flag for the MSHR of the cache above
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* where this packet originates from and guard noninitial
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* attempts to clear it.
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*
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* The flag markedPending needs to be updated when the
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* TargetList is in service which can be:
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* 1) during the Target instantiation if the MSHR is in
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* service and the target is not deferred,
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* 2) when the MSHR becomes in service if the target is not
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* deferred,
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* 3) or when the TargetList is promoted (deferredTargets ->
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* targets).
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*/
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bool markedPending;
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const bool allocOnFill; //!< Should the response servicing this
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//!< target list allocate in the cache?
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@ -296,6 +312,20 @@ class MSHR : public QueueEntry, public Printable
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int getNumTargets() const
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{ return targets.size() + deferredTargets.size(); }
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/**
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* Extracts the subset of the targets that can be serviced given a
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* received response. This function returns the targets list
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* unless the response is a ReadRespWithInvalidate. The
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* ReadRespWithInvalidate is only invalidating response that its
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* invalidation was not expected when the request (a
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* ReadSharedReq) was sent out. For ReadRespWithInvalidate we can
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* safely service only the first FromCPU target and all FromSnoop
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* targets (inform all snoopers that we no longer have the block).
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*
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* @param pkt The response from the downstream memory
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*/
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TargetList extractServiceableTargets(PacketPtr pkt);
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/**
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* Returns true if there are targets left.
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* @return true if there are targets
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