Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG-- extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
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2d029fe584
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3 changed files with 3 additions and 8 deletions
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@ -988,20 +988,19 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
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"instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
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head_inst->seqNum, head_inst->readPC());
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#if !FULL_SYSTEM
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// Hack to make sure syscalls/memory barriers/quiesces
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// aren't executed until all stores write back their data.
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// This direct communication shouldn't be used for
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// anything other than this.
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if (inst_num > 0 || iewStage->hasStoresToWB())
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#else
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if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
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head_inst->isQuiesce()) &&
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iewStage->hasStoresToWB())
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#endif
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{
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DPRINTF(Commit, "Waiting for all stores to writeback.\n");
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return false;
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} else if (inst_num > 0) {
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DPRINTF(Commit, "Waiting to become head of commit.\n");
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return false;
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}
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toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
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@ -1124,13 +1124,11 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
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}
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toRename->iewInfo[tid].dispatchedToLSQ++;
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#if FULL_SYSTEM
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} else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
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// Same as non-speculative stores.
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inst->setCanCommit();
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instQueue.insertBarrier(inst);
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add_to_iq = false;
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#endif
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} else if (inst->isNonSpeculative()) {
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DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
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"encountered, skipping.\n", tid);
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@ -509,7 +509,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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"storeHead: %i addr: %#x\n",
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load_idx, store_idx, storeHead, req->getPaddr());
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#if FULL_SYSTEM
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if (req->isLocked()) {
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// Disable recording the result temporarily. Writing to misc
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// regs normally updates the result, but this is not the
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@ -518,7 +517,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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TheISA::handleLockedRead(load_inst.get(), req);
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load_inst->recordResult = true;
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}
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#endif
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while (store_idx != -1) {
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// End once we've reached the top of the LSQ
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