Merge zizzer.eecs.umich.edu:/bk/m5
into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest --HG-- extra : convert_revision : 87387b4f896ed945196b2090484c932c8b7e5abc
This commit is contained in:
commit
0bbf9a4791
2 changed files with 24 additions and 6 deletions
|
@ -75,14 +75,17 @@
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
|
SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
|
||||||
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
|
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
SimpleCPU::TickEvent::process()
|
SimpleCPU::TickEvent::process()
|
||||||
{
|
{
|
||||||
cpu->tick();
|
int count = multiplier;
|
||||||
|
do {
|
||||||
|
cpu->tick();
|
||||||
|
} while (--count > 0 && cpu->status() == Running);
|
||||||
}
|
}
|
||||||
|
|
||||||
const char *
|
const char *
|
||||||
|
@ -269,6 +272,11 @@ SimpleCPU::regStats()
|
||||||
.desc("Number of memory references")
|
.desc("Number of memory references")
|
||||||
;
|
;
|
||||||
|
|
||||||
|
notIdleFraction
|
||||||
|
.name(name() + ".not_idle_fraction")
|
||||||
|
.desc("Percentage of non-idle cycles")
|
||||||
|
;
|
||||||
|
|
||||||
idleFraction
|
idleFraction
|
||||||
.name(name() + ".idle_fraction")
|
.name(name() + ".idle_fraction")
|
||||||
.desc("Percentage of idle cycles")
|
.desc("Percentage of idle cycles")
|
||||||
|
@ -799,6 +807,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||||
SimObjectParam<BaseMem *> dcache;
|
SimObjectParam<BaseMem *> dcache;
|
||||||
|
|
||||||
Param<bool> defer_registration;
|
Param<bool> defer_registration;
|
||||||
|
Param<int> multiplier;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||||
|
|
||||||
|
@ -830,7 +839,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||||
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
||||||
INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
|
INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
|
||||||
INIT_PARAM_DFLT(defer_registration, "defer registration with system "
|
INIT_PARAM_DFLT(defer_registration, "defer registration with system "
|
||||||
"(for sampling)", false)
|
"(for sampling)", false),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||||
|
|
||||||
|
@ -861,6 +872,8 @@ CREATE_SIM_OBJECT(SimpleCPU)
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
cpu->setTickMultiplier(multiplier);
|
||||||
|
|
||||||
return cpu;
|
return cpu;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -68,12 +68,11 @@ class SimpleCPU : public BaseCPU
|
||||||
void tick();
|
void tick();
|
||||||
|
|
||||||
private:
|
private:
|
||||||
class TickEvent : public Event
|
struct TickEvent : public Event
|
||||||
{
|
{
|
||||||
private:
|
|
||||||
SimpleCPU *cpu;
|
SimpleCPU *cpu;
|
||||||
|
int multiplier;
|
||||||
|
|
||||||
public:
|
|
||||||
TickEvent(SimpleCPU *c);
|
TickEvent(SimpleCPU *c);
|
||||||
void process();
|
void process();
|
||||||
const char *description();
|
const char *description();
|
||||||
|
@ -97,6 +96,12 @@ class SimpleCPU : public BaseCPU
|
||||||
tickEvent.squash();
|
tickEvent.squash();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public:
|
||||||
|
void setTickMultiplier(int multiplier)
|
||||||
|
{
|
||||||
|
tickEvent.multiplier = multiplier;
|
||||||
|
}
|
||||||
|
|
||||||
private:
|
private:
|
||||||
Trace::InstRecord *traceData;
|
Trace::InstRecord *traceData;
|
||||||
template<typename T>
|
template<typename T>
|
||||||
|
|
Loading…
Reference in a new issue