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Fix carry flag for subtracts, and clean up code slightly.

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--HG--
extra : convert_revision : 668f5d5aeba888488b41284de6c72a0d055c4ef4
This commit is contained in:
Gabe Black 2007-07-20 14:53:38 -07:00
parent 0781609693
commit 0baae59c09
1 changed files with 27 additions and 15 deletions
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42
src/arch/x86/isa/microops/regop.isa
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@ -309,7 +309,7 @@ let {{
exec_output = "" exec_output = ""
# A function which builds the C++ classes that implement the microops # A function which builds the C++ classes that implement the microops
def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck, elseCode): def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
global header_output global header_output
global decoder_output global decoder_output
global exec_output global exec_output
@ -331,7 +331,7 @@ let {{
# This creates a python representations of a microop which are a cross # This creates a python representations of a microop which are a cross
# product of reg/immediate and flag/no flag versions. # product of reg/immediate and flag/no flag versions.
def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False, elseCode=";"): def defineMicroRegOp(mnemonic, code, subtract = False, cc=False, elseCode=";"):
Name = mnemonic Name = mnemonic
name = mnemonic.lower() name = mnemonic.lower()
@ -342,6 +342,11 @@ let {{
regCode = matcher.sub("SrcReg2", code) regCode = matcher.sub("SrcReg2", code)
immCode = matcher.sub("imm8", code) immCode = matcher.sub("imm8", code)
if subtract:
secondSrc = "-op2, true"
else:
secondSrc = "op2"
if not cc: if not cc:
flagCode = genCCFlagBits % secondSrc flagCode = genCCFlagBits % secondSrc
condCode = "true" condCode = "true"
@ -360,8 +365,9 @@ let {{
microopClasses[name] = RegOpChild microopClasses[name] = RegOpChild
setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode); setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode, elseCode); setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
flagCode = regFlagCode, condCheck = condCode, elseCode = elseCode);
class RegOpChildImm(RegOpImm): class RegOpChildImm(RegOpImm):
mnemonic = name + 'i' mnemonic = name + 'i'
@ -371,17 +377,19 @@ let {{
microopClasses[name + 'i'] = RegOpChildImm microopClasses[name + 'i'] = RegOpChildImm
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode); setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode, elseCode); setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
defineMicroRegOp('mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
elseCode='DestReg=DestReg;', cc=True) elseCode='DestReg=DestReg;', cc=True)
@ -405,8 +413,9 @@ let {{
microopClasses[name] = RegOpChild microopClasses[name] = RegOpChild
setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode); setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits, elseCode); setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
condCheck = checkCCFlagBits, elseCode = elseCode);
class RegOpChildImm(RegOpImm): class RegOpChildImm(RegOpImm):
mnemonic = name + 'i' mnemonic = name + 'i'
@ -416,8 +425,9 @@ let {{
microopClasses[name + 'i'] = RegOpChildImm microopClasses[name + 'i'] = RegOpChildImm
setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode); setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits, elseCode); setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
condCheck = checkCCFlagBits, elseCode = elseCode);
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;") defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
@ -434,7 +444,7 @@ let {{
microopClasses[name] = RegOpChild microopClasses[name] = RegOpChild
setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true", ";"); setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
defineMicroRegOpRd('Rdip', 'DestReg = RIP') defineMicroRegOpRd('Rdip', 'DestReg = RIP')
@ -450,11 +460,13 @@ let {{
microopClasses[name] = RegOpChild microopClasses[name] = RegOpChild
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true", ";"); setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
defineMicroRegOpImm('Sext', ''' defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1; IntReg val = SrcReg1;
int sign_bit = bits(val, imm8-1, imm8-1); int sign_bit = bits(val, imm8-1, imm8-1);
val = sign_bit ? (val | ~mask(imm8)) : val; val = sign_bit ? (val | ~mask(imm8)) : val;
DestReg = merge(DestReg, val, dataSize);''') DestReg = merge(DestReg, val, dataSize);''')
defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
}}; }};