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Update EIO regressions for last set of patches

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This commit is contained in:
Ali Saidi 2010-11-10 00:48:03 -06:00
parent 14b27fc302
commit 0b7967d606
13 changed files with 1904 additions and 61 deletions
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2
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -53,7 +53,7 @@ type=ExeTracer
type=EioProcess type=EioProcess
chkpt= chkpt=
errout=cerr errout=cerr
file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None input=None
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout

18
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
View file

@ -1,9 +1,9 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> For more information see: http://www.m5sim.org/warn/d946bea6
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main warn: Prefetch instrutions is Alpha do not do anything
exec filecode in scope For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/run.py", line 78, in <module> warn: Prefetch instrutions is Alpha do not do anything
execfile(joinpath(tests_root, category, name, 'test.py')) For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/quick/20.eio-short/test.py", line 29, in <module> hack: be nice to actually delete the event here
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined gzip: stdout: Broken pipe

15
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,8 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Nov 9 2010 10:38:04
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision f4362ffd810f+ 7737+ default tip
M5 started Nov 2 2010 21:33:04 M5 started Nov 9 2010 22:11:58
M5 executing on aus-bc2-b15 M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 250015500 because a thread reached the max instruction count

50
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -0,0 +1,50 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2960881 # Simulator instruction rate (inst/s)
host_mem_usage 193980 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_tick_rate 1478428114 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 500032 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 500019 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 500032 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 180793 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------

18
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
View file

@ -1,9 +1,9 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> For more information see: http://www.m5sim.org/warn/d946bea6
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main warn: Prefetch instrutions is Alpha do not do anything
exec filecode in scope For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/run.py", line 78, in <module> warn: Prefetch instrutions is Alpha do not do anything
execfile(joinpath(tests_root, category, name, 'test.py')) For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/quick/20.eio-short/test.py", line 29, in <module> hack: be nice to actually delete the event here
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined gzip: stdout: Broken pipe

15
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,8 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Nov 9 2010 10:38:04
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision f4362ffd810f+ 7737+ default tip
M5 started Nov 2 2010 21:31:02 M5 started Nov 9 2010 22:11:58
M5 executing on aus-bc2-b15 M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 727929000 because a thread reached the max instruction count

233
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -0,0 +1,233 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1193890 # Simulator instruction rate (inst/s)
host_mem_usage 201748 # Number of bytes of host memory used
host_seconds 0.42 # Real time elapsed on the host
host_tick_rate 1737027103 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000728 # Number of seconds simulated
sim_ticks 727929000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180321 # number of overall hits
system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_misses 454 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499617 # number of overall hits
system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_misses 403 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 500033 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 500020 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 857 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1455858 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 180793 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------

24
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -1,9 +1,15 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> For more information see: http://www.m5sim.org/warn/d946bea6
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main warn: Prefetch instrutions is Alpha do not do anything
exec filecode in scope For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/run.py", line 78, in <module> warn: Prefetch instrutions is Alpha do not do anything
execfile(joinpath(tests_root, category, name, 'test.py')) For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/quick/30.eio-mp/test.py", line 29, in <module> hack: be nice to actually delete the event here
process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
NameError: name 'EioProcess' is not defined gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe

21
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,8 +5,19 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Nov 9 2010 10:38:04
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision f4362ffd810f+ 7737+ default tip
M5 started Nov 2 2010 21:31:02 M5 started Nov 9 2010 22:11:58
M5 executing on aus-bc2-b15 M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 250015500 because a thread reached the max instruction count

712
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

@ -0,0 +1,712 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2770469 # Simulator instruction rate (inst/s)
host_mem_usage 1126824 # Number of bytes of host memory used
host_seconds 0.72 # Real time elapsed on the host
host_tick_rate 346193150 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits 180312 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_misses 463 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 61 # number of replacements
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 29 # number of writebacks
system.cpu0.dtb.data_accesses 180793 # DTB accesses
system.cpu0.dtb.data_acv 0 # DTB access violations
system.cpu0.dtb.data_hits 180775 # DTB hits
system.cpu0.dtb.data_misses 18 # DTB misses
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.read_accesses 124443 # DTB read accesses
system.cpu0.dtb.read_acv 0 # DTB read access violations
system.cpu0.dtb.read_hits 124435 # DTB read hits
system.cpu0.dtb.read_misses 8 # DTB read misses
system.cpu0.dtb.write_accesses 56350 # DTB write accesses
system.cpu0.dtb.write_acv 0 # DTB write access violations
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits 499556 # number of overall hits
system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_misses 463 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements 152 # number of replacements
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.fetch_accesses 500032 # ITB accesses
system.cpu0.itb.fetch_acv 0 # ITB acv
system.cpu0.itb.fetch_hits 500019 # ITB hits
system.cpu0.itb.fetch_misses 13 # ITB misses
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.numCycles 500032 # number of cpu cycles simulated
system.cpu0.num_insts 500001 # Number of instructions executed
system.cpu0.num_refs 180793 # Number of memory references
system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits 180312 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 463 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements 61 # number of replacements
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 29 # number of writebacks
system.cpu1.dtb.data_accesses 180793 # DTB accesses
system.cpu1.dtb.data_acv 0 # DTB access violations
system.cpu1.dtb.data_hits 180775 # DTB hits
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_hits 124435 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
system.cpu1.dtb.write_accesses 56350 # DTB write accesses
system.cpu1.dtb.write_acv 0 # DTB write access violations
system.cpu1.dtb.write_hits 56340 # DTB write hits
system.cpu1.dtb.write_misses 10 # DTB write misses
system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits 499556 # number of overall hits
system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu1.icache.overall_misses 463 # number of overall misses
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements 152 # number of replacements
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.fetch_accesses 500032 # ITB accesses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_hits 500019 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.numCycles 500032 # number of cpu cycles simulated
system.cpu1.num_insts 500001 # Number of instructions executed
system.cpu1.num_refs 180793 # Number of memory references
system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits 180312 # number of overall hits
system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu2.dcache.overall_misses 463 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements 61 # number of replacements
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 29 # number of writebacks
system.cpu2.dtb.data_accesses 180793 # DTB accesses
system.cpu2.dtb.data_acv 0 # DTB access violations
system.cpu2.dtb.data_hits 180775 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.read_accesses 124443 # DTB read accesses
system.cpu2.dtb.read_acv 0 # DTB read access violations
system.cpu2.dtb.read_hits 124435 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.write_accesses 56350 # DTB write accesses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_hits 56340 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits 499556 # number of overall hits
system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu2.icache.overall_misses 463 # number of overall misses
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements 152 # number of replacements
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.fetch_accesses 500032 # ITB accesses
system.cpu2.itb.fetch_acv 0 # ITB acv
system.cpu2.itb.fetch_hits 500019 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.numCycles 500032 # number of cpu cycles simulated
system.cpu2.num_insts 500001 # Number of instructions executed
system.cpu2.num_refs 180793 # Number of memory references
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits 180312 # number of overall hits
system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu3.dcache.overall_misses 463 # number of overall misses
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements 61 # number of replacements
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 29 # number of writebacks
system.cpu3.dtb.data_accesses 180793 # DTB accesses
system.cpu3.dtb.data_acv 0 # DTB access violations
system.cpu3.dtb.data_hits 180775 # DTB hits
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.read_accesses 124443 # DTB read accesses
system.cpu3.dtb.read_acv 0 # DTB read access violations
system.cpu3.dtb.read_hits 124435 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.write_accesses 56350 # DTB write accesses
system.cpu3.dtb.write_acv 0 # DTB write access violations
system.cpu3.dtb.write_hits 56340 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits 499556 # number of overall hits
system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu3.icache.overall_misses 463 # number of overall misses
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements 152 # number of replacements
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
system.cpu3.idle_fraction 0 # Percentage of idle cycles
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_hits 0 # DTB hits
system.cpu3.itb.data_misses 0 # DTB misses
system.cpu3.itb.fetch_accesses 500032 # ITB accesses
system.cpu3.itb.fetch_acv 0 # ITB acv
system.cpu3.itb.fetch_hits 500019 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.read_acv 0 # DTB read access violations
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_accesses 0 # DTB write accesses
system.cpu3.itb.write_acv 0 # DTB write access violations
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.numCycles 500032 # number of cpu cycles simulated
system.cpu3.num_insts 500001 # Number of instructions executed
system.cpu3.num_refs 180793 # Number of memory references
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 718 # number of ReadReq misses
system.l2c.ReadReq_misses::1 718 # number of ReadReq misses
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.demand_hits::0 69 # number of demand (read+write) hits
system.l2c.demand_hits::1 69 # number of demand (read+write) hits
system.l2c.demand_hits::2 69 # number of demand (read+write) hits
system.l2c.demand_hits::3 69 # number of demand (read+write) hits
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
system.l2c.demand_misses::0 857 # number of demand (read+write) misses
system.l2c.demand_misses::1 857 # number of demand (read+write) misses
system.l2c.demand_misses::2 857 # number of demand (read+write) misses
system.l2c.demand_misses::3 857 # number of demand (read+write) misses
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 69 # number of overall hits
system.l2c.overall_hits::1 69 # number of overall hits
system.l2c.overall_hits::2 69 # number of overall hits
system.l2c.overall_hits::3 69 # number of overall hits
system.l2c.overall_hits::total 276 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
system.l2c.overall_misses::0 857 # number of overall misses
system.l2c.overall_misses::1 857 # number of overall misses
system.l2c.overall_misses::2 857 # number of overall misses
system.l2c.overall_misses::3 857 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------

24
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
View file

@ -1,9 +1,15 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> For more information see: http://www.m5sim.org/warn/d946bea6
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main warn: Prefetch instrutions is Alpha do not do anything
exec filecode in scope For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/run.py", line 78, in <module> warn: Prefetch instrutions is Alpha do not do anything
execfile(joinpath(tests_root, category, name, 'test.py')) For more information see: http://www.m5sim.org/warn/3e0eccba
File "tests/quick/30.eio-mp/test.py", line 29, in <module> hack: be nice to actually delete the event here
process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
NameError: name 'EioProcess' is not defined gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe

21
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,8 +5,19 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Nov 9 2010 10:38:04
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision f4362ffd810f+ 7737+ default tip
M5 started Nov 2 2010 21:33:05 M5 started Nov 9 2010 22:11:58
M5 executing on aus-bc2-b15 M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 728920000 because a thread reached the max instruction count

812
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

@ -0,0 +1,812 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1961801 # Simulator instruction rate (inst/s)
host_mem_usage 209312 # Number of bytes of host memory used
host_seconds 1.02 # Real time elapsed on the host
host_tick_rate 714851017 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1999954 # Number of instructions simulated
sim_seconds 0.000729 # Number of seconds simulated
sim_ticks 728920000 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits 180312 # number of overall hits
system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_misses 463 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 61 # number of replacements
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 29 # number of writebacks
system.cpu0.dtb.data_accesses 180793 # DTB accesses
system.cpu0.dtb.data_acv 0 # DTB access violations
system.cpu0.dtb.data_hits 180775 # DTB hits
system.cpu0.dtb.data_misses 18 # DTB misses
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.read_accesses 124443 # DTB read accesses
system.cpu0.dtb.read_acv 0 # DTB read access violations
system.cpu0.dtb.read_hits 124435 # DTB read hits
system.cpu0.dtb.read_misses 8 # DTB read misses
system.cpu0.dtb.write_accesses 56350 # DTB write accesses
system.cpu0.dtb.write_acv 0 # DTB write access violations
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits 499557 # number of overall hits
system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_misses 463 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements 152 # number of replacements
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.fetch_accesses 500033 # ITB accesses
system.cpu0.itb.fetch_acv 0 # ITB acv
system.cpu0.itb.fetch_hits 500020 # ITB hits
system.cpu0.itb.fetch_misses 13 # ITB misses
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.numCycles 1457840 # number of cpu cycles simulated
system.cpu0.num_insts 500001 # Number of instructions executed
system.cpu0.num_refs 180793 # Number of memory references
system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context
system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits 180311 # number of overall hits
system.cpu1.dcache.overall_miss_latency 25588000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 463 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements 61 # number of replacements
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use
system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 29 # number of writebacks
system.cpu1.dtb.data_accesses 180792 # DTB accesses
system.cpu1.dtb.data_acv 0 # DTB access violations
system.cpu1.dtb.data_hits 180774 # DTB hits
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_hits 124435 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
system.cpu1.dtb.write_acv 0 # DTB write access violations
system.cpu1.dtb.write_hits 56339 # DTB write hits
system.cpu1.dtb.write_misses 10 # DTB write misses
system.cpu1.icache.ReadReq_accesses 500012 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits 499549 # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency 23473000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_miss_latency 22084000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.demand_accesses 500012 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 50697.624190 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
system.cpu1.icache.demand_hits 499549 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 23473000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 22084000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context
system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits 499549 # number of overall hits
system.cpu1.icache.overall_miss_latency 23473000 # number of overall miss cycles
system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu1.icache.overall_misses 463 # number of overall misses
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 22084000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements 152 # number of replacements
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use
system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.fetch_accesses 500025 # ITB accesses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_hits 500012 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.numCycles 1457840 # number of cpu cycles simulated
system.cpu1.num_insts 499993 # Number of instructions executed
system.cpu1.num_refs 180792 # Number of memory references
system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 24202000 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context
system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits 180309 # number of overall hits
system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu2.dcache.overall_misses 463 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 24202000 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements 61 # number of replacements
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use
system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 29 # number of writebacks
system.cpu2.dtb.data_accesses 180790 # DTB accesses
system.cpu2.dtb.data_acv 0 # DTB access violations
system.cpu2.dtb.data_hits 180772 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.read_accesses 124441 # DTB read accesses
system.cpu2.dtb.read_acv 0 # DTB read access violations
system.cpu2.dtb.read_hits 124433 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context
system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits 499538 # number of overall hits
system.cpu2.icache.overall_miss_latency 23483000 # number of overall miss cycles
system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu2.icache.overall_misses 463 # number of overall misses
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements 152 # number of replacements
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use
system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.fetch_accesses 500014 # ITB accesses
system.cpu2.itb.fetch_acv 0 # ITB acv
system.cpu2.itb.fetch_hits 500001 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.numCycles 1457840 # number of cpu cycles simulated
system.cpu2.num_insts 499982 # Number of instructions executed
system.cpu2.num_refs 180789 # Number of memory references
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_hits 124107 # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.demand_accesses 180770 # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
system.cpu3.dcache.demand_hits 180307 # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context
system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits 180307 # number of overall hits
system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
system.cpu3.dcache.overall_misses 463 # number of overall misses
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements 61 # number of replacements
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use
system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 29 # number of writebacks
system.cpu3.dtb.data_accesses 180788 # DTB accesses
system.cpu3.dtb.data_acv 0 # DTB access violations
system.cpu3.dtb.data_hits 180770 # DTB hits
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.read_accesses 124439 # DTB read accesses
system.cpu3.dtb.read_acv 0 # DTB read access violations
system.cpu3.dtb.read_hits 124431 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
system.cpu3.dtb.write_acv 0 # DTB write access violations
system.cpu3.dtb.write_hits 56339 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits 499534 # number of overall hits
system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu3.icache.overall_misses 463 # number of overall misses
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements 152 # number of replacements
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
system.cpu3.idle_fraction 0 # Percentage of idle cycles
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_hits 0 # DTB hits
system.cpu3.itb.data_misses 0 # DTB misses
system.cpu3.itb.fetch_accesses 500010 # ITB accesses
system.cpu3.itb.fetch_acv 0 # ITB acv
system.cpu3.itb.fetch_hits 499997 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.read_acv 0 # DTB read access violations
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_accesses 0 # DTB write accesses
system.cpu3.itb.write_acv 0 # DTB write access violations
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.numCycles 1457840 # number of cpu cycles simulated
system.cpu3.num_insts 499978 # Number of instructions executed
system.cpu3.num_refs 180787 # Number of memory references
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 718 # number of ReadReq misses
system.l2c.ReadReq_misses::1 718 # number of ReadReq misses
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency
system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
system.l2c.demand_hits::0 69 # number of demand (read+write) hits
system.l2c.demand_hits::1 69 # number of demand (read+write) hits
system.l2c.demand_hits::2 69 # number of demand (read+write) hits
system.l2c.demand_hits::3 69 # number of demand (read+write) hits
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
system.l2c.demand_misses::0 857 # number of demand (read+write) misses
system.l2c.demand_misses::1 857 # number of demand (read+write) misses
system.l2c.demand_misses::2 857 # number of demand (read+write) misses
system.l2c.demand_misses::3 857 # number of demand (read+write) misses
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 14.807775 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context
system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context
system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context
system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context
system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency
system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 69 # number of overall hits
system.l2c.overall_hits::1 69 # number of overall hits
system.l2c.overall_hits::2 69 # number of overall hits
system.l2c.overall_hits::3 69 # number of overall hits
system.l2c.overall_hits::total 276 # number of overall hits
system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
system.l2c.overall_misses::0 857 # number of overall misses
system.l2c.overall_misses::1 857 # number of overall misses
system.l2c.overall_misses::2 857 # number of overall misses
system.l2c.overall_misses::3 857 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------