O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
This commit is contained in:
parent
5a648f2074
commit
0b3897fc90
18 changed files with 117 additions and 37 deletions
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@ -43,6 +43,7 @@
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/Drain.hh"
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#include "debug/TLB.hh"
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#include "debug/TLBVerbose.hh"
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#include "sim/system.hh"
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@ -51,7 +52,7 @@ using namespace ArmISA;
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TableWalker::TableWalker(const Params *p)
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: MemObject(p), port(this, params()->sys, params()->min_backoff,
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params()->max_backoff),
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params()->max_backoff), drainEvent(NULL),
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tlb(NULL), currState(NULL), pending(false),
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masterId(p->sys->getMasterId(name())),
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doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
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@ -64,20 +65,38 @@ TableWalker::~TableWalker()
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;
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}
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void
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TableWalker::completeDrain()
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{
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if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() &&
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pendingQueue.empty()) {
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changeState(Drained);
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DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
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drainEvent->process();
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drainEvent = NULL;
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}
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}
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unsigned int
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TableWalker::drain(Event *de)
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{
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if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
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{
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changeState(Draining);
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DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
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return 1;
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}
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else
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{
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unsigned int count = port.drain(de);
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if (stateQueueL1.empty() && stateQueueL2.empty() &&
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pendingQueue.empty()) {
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changeState(Drained);
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DPRINTF(Checkpoint, "TableWalker free, no need to drain\n");
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return 0;
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DPRINTF(Drain, "TableWalker free, no need to drain\n");
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// table walker is drained, but its ports may still need to be drained
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return count;
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} else {
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drainEvent = de;
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changeState(Draining);
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DPRINTF(Drain, "TableWalker not drained\n");
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// return port drain count plus the table walker itself needs to drain
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return count + 1;
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}
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}
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@ -86,8 +105,8 @@ TableWalker::resume()
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{
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MemObject::resume();
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if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
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delete currState;
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currState = NULL;
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delete currState;
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currState = NULL;
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}
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}
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@ -667,6 +686,7 @@ TableWalker::doL1DescriptorWrapper()
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doL1Descriptor();
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stateQueueL1.pop_front();
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completeDrain();
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// Check if fault was generated
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if (currState->fault != NoFault) {
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currState->transState->finish(currState->fault, currState->req,
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@ -723,6 +743,7 @@ TableWalker::doL2DescriptorWrapper()
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stateQueueL2.pop_front();
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completeDrain();
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pending = false;
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nextWalk(currState->tc);
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@ -364,6 +364,9 @@ class TableWalker : public MemObject
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/** Port to issue translation requests from */
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SnoopingDmaPort port;
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/** If we're draining keep the drain event around until we're drained */
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Event *drainEvent;
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/** TLB that is initiating these table walks */
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TLB *tlb;
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@ -389,6 +392,8 @@ class TableWalker : public MemObject
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return dynamic_cast<const Params *>(_params);
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}
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/** Checks if all state is cleared and if so, completes drain */
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void completeDrain();
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virtual unsigned int drain(Event *de);
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virtual void resume();
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virtual MasterPort& getMasterPort(const std::string &if_name,
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@ -385,8 +385,7 @@ void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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_cpuId = oldCPU->cpuId();
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assert(_cpuId == oldCPU->cpuId());
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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@ -418,11 +417,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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assert(old_itb_port);
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SlavePort &slavePort = old_itb_port->getSlavePort();
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new_itb_port->bind(slavePort);
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old_itb_port->unBind();
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}
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if (new_dtb_port && !new_dtb_port->isConnected()) {
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assert(old_dtb_port);
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SlavePort &slavePort = old_dtb_port->getSlavePort();
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new_dtb_port->bind(slavePort);
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old_dtb_port->unBind();
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}
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// Checker whether or not we have to transfer CheckerCPU
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@ -444,17 +445,20 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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assert(old_checker_itb_port);
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SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
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new_checker_itb_port->bind(slavePort);
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old_checker_itb_port->unBind();
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}
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if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
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assert(old_checker_dtb_port);
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SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
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new_checker_dtb_port->bind(slavePort);
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old_checker_dtb_port->unBind();
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}
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}
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}
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interrupts = oldCPU->interrupts;
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interrupts->setCPU(this);
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oldCPU->interrupts = NULL;
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if (FullSystem) {
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for (ThreadID i = 0; i < size; ++i)
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@ -469,10 +473,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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// CPU.
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if (!getInstPort().isConnected()) {
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getInstPort().bind(oldCPU->getInstPort().getSlavePort());
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oldCPU->getInstPort().unBind();
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}
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if (!getDataPort().isConnected()) {
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getDataPort().bind(oldCPU->getDataPort().getSlavePort());
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oldCPU->getDataPort().unBind();
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}
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}
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@ -631,7 +631,8 @@ DefaultCommit<Impl>::tick()
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wroteToTimeBuffer = false;
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_nextStatus = Inactive;
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if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
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if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
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interrupt == NoFault) {
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cpu->signalDrained();
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drainPending = false;
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return;
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@ -55,6 +55,7 @@
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Activity.hh"
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#include "debug/Drain.hh"
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#include "debug/O3CPU.hh"
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#include "debug/Quiesce.hh"
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#include "enums/MemoryMode.hh"
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@ -260,7 +261,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
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if (!deferRegistration) {
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_status = Running;
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} else {
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_status = Idle;
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_status = SwitchedOut;
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}
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if (params->checker) {
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@ -1119,9 +1120,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
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DPRINTF(O3CPU, "Switching out\n");
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// If the CPU isn't doing anything, then return immediately.
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if (_status == Idle || _status == SwitchedOut) {
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if (_status == SwitchedOut)
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return 0;
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}
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drainCount = 0;
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fetch.drain();
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@ -1142,6 +1142,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
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wakeCPU();
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activityRec.activity();
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DPRINTF(Drain, "CPU not drained\n");
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return 1;
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} else {
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return 0;
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@ -1160,7 +1162,7 @@ FullO3CPU<Impl>::resume()
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changeState(SimObject::Running);
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if (_status == SwitchedOut || _status == Idle)
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if (_status == SwitchedOut)
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return;
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assert(system->getMemoryMode() == Enums::timing);
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@ -1183,6 +1185,7 @@ FullO3CPU<Impl>::signalDrained()
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BaseCPU::switchOut();
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if (drainEvent) {
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DPRINTF(Drain, "CPU done draining, processing drain event\n");
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drainEvent->process();
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drainEvent = NULL;
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}
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@ -1237,6 +1240,10 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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assert(!tickEvent.scheduled() || tickEvent.squashed());
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FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
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if (oldO3CPU)
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globalSeqNum = oldO3CPU->globalSeqNum;
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// @todo: Figure out how to properly select the tid to put onto
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// the active threads list.
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ThreadID tid = 0;
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@ -132,8 +132,10 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
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// Get the size of an instruction.
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instSize = sizeof(TheISA::MachInst);
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for (int i = 0; i < Impl::MaxThreads; i++)
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for (int i = 0; i < Impl::MaxThreads; i++) {
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cacheData[i] = NULL;
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decoder[i] = new TheISA::Decoder(NULL);
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}
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}
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template <class Impl>
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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if (!cacheData[tid])
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cacheData[tid] = new uint8_t[cacheBlkSize];
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cacheDataPC[tid] = 0;
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cacheDataValid[tid] = false;
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}
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@ -335,6 +335,11 @@ class LSQUnit {
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std::memset(data, 0, sizeof(data));
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}
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~SQEntry()
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{
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inst = NULL;
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}
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/** Constructs a store queue entry for a given instruction. */
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SQEntry(DynInstPtr &_inst)
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: inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
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@ -48,6 +48,7 @@
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#include "cpu/simple/timing.hh"
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#include "cpu/exetrace.hh"
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#include "debug/Config.hh"
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#include "debug/Drain.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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#include "mem/packet.hh"
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@ -129,6 +130,7 @@ TimingSimpleCPU::drain(Event *drain_event)
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} else {
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changeState(SimObject::Draining);
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drainEvent = drain_event;
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DPRINTF(Drain, "CPU not drained\n");
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return 1;
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}
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}
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@ -829,7 +831,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
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void
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TimingSimpleCPU::completeDrain()
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{
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DPRINTF(Config, "Done draining\n");
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DPRINTF(Drain, "CPU done draining, processing drain event\n");
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changeState(SimObject::Drained);
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drainEvent->process();
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}
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@ -49,6 +49,7 @@
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#include "base/cp_annotate.hh"
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#include "base/trace.hh"
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#include "debug/DMACopyEngine.hh"
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#include "debug/Drain.hh"
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#include "dev/copy_engine.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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@ -638,7 +639,7 @@ bool
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CopyEngine::CopyEngineChannel::inDrain()
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{
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if (ce->getState() == SimObject::Draining) {
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DPRINTF(DMACopyEngine, "processing drain\n");
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DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
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assert(drainEvent);
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drainEvent->process();
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drainEvent = NULL;
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@ -655,7 +656,7 @@ CopyEngine::CopyEngineChannel::drain(Event *de)
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unsigned int count = 1;
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count += cePort.drain(de);
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DPRINTF(DMACopyEngine, "unable to drain, returning %d\n", count);
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DPRINTF(Drain, "CopyEngineChannel not drained\n");
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drainEvent = de;
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return count;
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}
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else
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changeState(Drained);
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DPRINTF(DMACopyEngine, "call to CopyEngine::drain() returning %d\n", count);
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DPRINTF(Drain, "CopyEngine not drained\n");
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return count;
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}
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@ -43,6 +43,7 @@
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#include "base/chunk_generator.hh"
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#include "debug/DMA.hh"
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#include "debug/Drain.hh"
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#include "dev/dma_device.hh"
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#include "sim/system.hh"
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@ -103,7 +104,7 @@ DmaPort::recvTimingResp(PacketPtr pkt)
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delete pkt->req;
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delete pkt;
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if (pendingCount == 0 && drainEvent) {
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if (pendingCount == 0 && transmitList.empty() && drainEvent) {
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drainEvent->process();
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drainEvent = NULL;
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}
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@ -142,9 +143,10 @@ DmaDevice::drain(Event *de)
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unsigned int
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DmaPort::drain(Event *de)
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{
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if (pendingCount == 0)
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if (transmitList.empty() && pendingCount == 0)
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return 0;
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drainEvent = de;
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DPRINTF(Drain, "DmaPort not drained\n");
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return 1;
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}
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data, Tick delay, Request::Flags flag)
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{
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assert(device->getState() == SimObject::Running);
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DmaReqState *reqState = new DmaReqState(event, size, delay);
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assert(pendingCount >= 0);
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delete pkt;
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if (pendingCount == 0 && drainEvent) {
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if (pendingCount == 0 && transmitList.empty() && drainEvent) {
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DPRINTF(Drain, "DmaPort done draining, processing drain event\n");
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drainEvent->process();
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drainEvent = NULL;
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}
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@ -44,6 +44,7 @@
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#include "base/inet.hh"
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#include "base/trace.hh"
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#include "debug/Drain.hh"
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#include "debug/EthernetAll.hh"
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#include "dev/i8254xGBe.hh"
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#include "mem/packet.hh"
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@ -2072,12 +2073,12 @@ IGbE::drain(Event *de)
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if (tickEvent.scheduled())
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deschedule(tickEvent);
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if (count)
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if (count) {
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DPRINTF(Drain, "IGbE not drained\n");
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changeState(Draining);
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else
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} else
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changeState(Drained);
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DPRINTF(EthernetSM, "got drain() returning %d", count);
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return count;
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}
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if (!drainEvent)
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return;
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DPRINTF(EthernetSM, "checkDrain() in drain\n");
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txFifoTick = false;
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txTick = false;
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rxTick = false;
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if (!rxDescCache.hasOutstandingEvents() &&
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!txDescCache.hasOutstandingEvents()) {
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DPRINTF(Drain, "IGbE done draining, processing drain event\n");
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drainEvent->process();
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drainEvent = NULL;
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}
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@ -52,6 +52,7 @@
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#include "base/trace.hh"
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#include "debug/Bus.hh"
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#include "debug/BusAddrRanges.hh"
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#include "debug/Drain.hh"
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#include "mem/bus.hh"
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BaseBus::BaseBus(const BaseBusParams *p)
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@ -246,6 +247,7 @@ BaseBus::Layer<PortClass>::releaseLayer()
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// we see a retry from the destination
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retryWaiting();
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} else if (drainEvent) {
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DPRINTF(Drain, "Bus done draining, processing drain event\n");
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//If we weren't able to drain before, do it now.
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drainEvent->process();
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// Clear the drain event once we're done with it.
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@ -498,6 +500,7 @@ BaseBus::Layer<PortClass>::drain(Event * de)
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//waiting. We might be idle but have someone waiting if the device we
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//contacted for a retry didn't actually retry.
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if (!retryList.empty() || state != IDLE) {
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DPRINTF(Drain, "Bus not drained\n");
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drainEvent = de;
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return 1;
|
||||
}
|
||||
|
|
2
src/mem/cache/base.cc
vendored
2
src/mem/cache/base.cc
vendored
|
@ -48,6 +48,7 @@
|
|||
#include "cpu/base.hh"
|
||||
#include "cpu/smt.hh"
|
||||
#include "debug/Cache.hh"
|
||||
#include "debug/Drain.hh"
|
||||
#include "mem/cache/base.hh"
|
||||
#include "mem/cache/mshr.hh"
|
||||
#include "sim/full_system.hh"
|
||||
|
@ -752,6 +753,7 @@ BaseCache::drain(Event *de)
|
|||
drainEvent = de;
|
||||
|
||||
changeState(SimObject::Draining);
|
||||
DPRINTF(Drain, "Cache not drained\n");
|
||||
return count;
|
||||
}
|
||||
|
||||
|
|
|
@ -41,6 +41,7 @@
|
|||
* Andreas Hansson
|
||||
*/
|
||||
|
||||
#include "debug/Drain.hh"
|
||||
#include "debug/PacketQueue.hh"
|
||||
#include "mem/packet_queue.hh"
|
||||
|
||||
|
@ -168,7 +169,9 @@ PacketQueue::scheduleSend(Tick time)
|
|||
em.schedule(&sendEvent, std::max(nextReady, curTick() + 1));
|
||||
} else {
|
||||
// no more to send, so if we're draining, we may be done
|
||||
if (drainEvent && !sendEvent.scheduled()) {
|
||||
if (drainEvent && transmitList.empty() && !sendEvent.scheduled()) {
|
||||
DPRINTF(Drain, "PacketQueue done draining,"
|
||||
"processing drain event\n");
|
||||
drainEvent->process();
|
||||
drainEvent = NULL;
|
||||
}
|
||||
|
@ -201,6 +204,7 @@ PacketQueue::drain(Event *de)
|
|||
{
|
||||
if (transmitList.empty() && !sendEvent.scheduled())
|
||||
return 0;
|
||||
DPRINTF(Drain, "PacketQueue not drained\n");
|
||||
drainEvent = de;
|
||||
return 1;
|
||||
}
|
||||
|
|
|
@ -81,6 +81,12 @@ MasterPort::getSlavePort() const
|
|||
return *_slavePort;
|
||||
}
|
||||
|
||||
void
|
||||
MasterPort::unBind()
|
||||
{
|
||||
_slavePort = NULL;
|
||||
}
|
||||
|
||||
void
|
||||
MasterPort::bind(SlavePort& slave_port)
|
||||
{
|
||||
|
@ -166,6 +172,12 @@ SlavePort::~SlavePort()
|
|||
{
|
||||
}
|
||||
|
||||
void
|
||||
SlavePort::unBind()
|
||||
{
|
||||
_masterPort = NULL;
|
||||
}
|
||||
|
||||
void
|
||||
SlavePort::bind(MasterPort& master_port)
|
||||
{
|
||||
|
|
|
@ -140,6 +140,7 @@ class MasterPort : public Port
|
|||
PortID id = InvalidPortID);
|
||||
virtual ~MasterPort();
|
||||
|
||||
void unBind();
|
||||
void bind(SlavePort& slave_port);
|
||||
SlavePort& getSlavePort() const;
|
||||
bool isConnected() const;
|
||||
|
@ -297,6 +298,7 @@ class SlavePort : public Port
|
|||
PortID id = InvalidPortID);
|
||||
virtual ~SlavePort();
|
||||
|
||||
void unBind();
|
||||
void bind(MasterPort& master_port);
|
||||
MasterPort& getMasterPort() const;
|
||||
bool isConnected() const;
|
||||
|
|
|
@ -41,6 +41,7 @@
|
|||
|
||||
#include "cpu/testers/rubytest/RubyTester.hh"
|
||||
#include "debug/Config.hh"
|
||||
#include "debug/Drain.hh"
|
||||
#include "debug/Ruby.hh"
|
||||
#include "mem/protocol/AccessPermission.hh"
|
||||
#include "mem/ruby/slicc_interface/AbstractController.hh"
|
||||
|
@ -524,8 +525,9 @@ RubyPort::testDrainComplete()
|
|||
//If we weren't able to drain before, we might be able to now.
|
||||
if (drainEvent != NULL) {
|
||||
unsigned int drainCount = getDrainCount(drainEvent);
|
||||
DPRINTF(Config, "Drain count: %u\n", drainCount);
|
||||
DPRINTF(Drain, "Drain count: %u\n", drainCount);
|
||||
if (drainCount == 0) {
|
||||
DPRINTF(Drain, "RubyPort done draining, processing drain event\n");
|
||||
drainEvent->process();
|
||||
// Clear the drain event once we're done with it.
|
||||
drainEvent = NULL;
|
||||
|
@ -584,6 +586,7 @@ RubyPort::drain(Event *de)
|
|||
if (count != 0) {
|
||||
drainEvent = de;
|
||||
|
||||
DPRINTF(Drain, "RubyPort not drained\n");
|
||||
changeState(SimObject::Draining);
|
||||
return count;
|
||||
}
|
||||
|
|
|
@ -62,6 +62,7 @@ if env['TARGET_ISA'] != 'no':
|
|||
|
||||
DebugFlag('Checkpoint')
|
||||
DebugFlag('Config')
|
||||
DebugFlag('Drain')
|
||||
DebugFlag('Event')
|
||||
DebugFlag('Fault')
|
||||
DebugFlag('Flow')
|
||||
|
|
Loading…
Reference in a new issue