alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
This commit is contained in:
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819023b8e2
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0b30c345f1
11 changed files with 35 additions and 39 deletions
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@ -44,9 +44,9 @@
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#include "sim/debug.hh"
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#include "sim/debug.hh"
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#include "sim/sim_exit.hh"
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#include "sim/sim_exit.hh"
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#if FULL_SYSTEM
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using namespace AlphaISA;
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using namespace EV5;
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#if FULL_SYSTEM
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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@ -146,13 +146,13 @@ SimpleThread::hwrei()
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int
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int
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AlphaISA::MiscRegFile::getInstAsid()
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AlphaISA::MiscRegFile::getInstAsid()
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{
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{
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return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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}
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}
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int
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int
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AlphaISA::MiscRegFile::getDataAsid()
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AlphaISA::MiscRegFile::getDataAsid()
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{
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{
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return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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}
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}
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#endif
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#endif
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@ -168,7 +168,7 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
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tc->setMiscRegNoEffect(i, 0);
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tc->setMiscRegNoEffect(i, 0);
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}
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}
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tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
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tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
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tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
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tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
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tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
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tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
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}
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}
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@ -477,27 +477,27 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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ipr[idx] = val;
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ipr[idx] = val;
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tc->getDTBPtr()->flushAddr(val,
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tc->getDTBPtr()->flushAddr(val,
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EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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break;
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break;
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case AlphaISA::IPR_DTB_TAG: {
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case AlphaISA::IPR_DTB_TAG: {
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struct AlphaISA::TlbEntry entry;
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struct AlphaISA::TlbEntry entry;
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// FIXME: granularity hints NYI...
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// FIXME: granularity hints NYI...
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if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
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if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
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panic("PTE GH field != 0");
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panic("PTE GH field != 0");
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// write entire quad
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// write entire quad
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ipr[idx] = val;
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ipr[idx] = val;
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// construct PTE for new entry
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// construct PTE for new entry
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entry.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
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entry.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
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entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
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// insert new TAG/PTE value into data TLB
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// insert new TAG/PTE value into data TLB
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tc->getDTBPtr()->insert(val, entry);
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tc->getDTBPtr()->insert(val, entry);
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@ -508,20 +508,20 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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struct AlphaISA::TlbEntry entry;
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struct AlphaISA::TlbEntry entry;
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// FIXME: granularity hints NYI...
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// FIXME: granularity hints NYI...
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if (EV5::ITB_PTE_GH(val) != 0)
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if (AlphaISA::ITB_PTE_GH(val) != 0)
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panic("PTE GH field != 0");
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panic("PTE GH field != 0");
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// write entire quad
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// write entire quad
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ipr[idx] = val;
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ipr[idx] = val;
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// construct PTE for new entry
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// construct PTE for new entry
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entry.ppn = EV5::ITB_PTE_PPN(val);
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entry.ppn = AlphaISA::ITB_PTE_PPN(val);
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entry.xre = EV5::ITB_PTE_XRE(val);
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entry.xre = AlphaISA::ITB_PTE_XRE(val);
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entry.xwe = 0;
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entry.xwe = 0;
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entry.fonr = EV5::ITB_PTE_FONR(val);
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entry.fonr = AlphaISA::ITB_PTE_FONR(val);
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entry.fonw = EV5::ITB_PTE_FONW(val);
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entry.fonw = AlphaISA::ITB_PTE_FONW(val);
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entry.asma = EV5::ITB_PTE_ASMA(val);
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entry.asma = AlphaISA::ITB_PTE_ASMA(val);
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entry.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
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entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
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// insert new TAG/PTE value into data TLB
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// insert new TAG/PTE value into data TLB
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tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
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tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
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@ -547,7 +547,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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ipr[idx] = val;
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ipr[idx] = val;
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tc->getITBPtr()->flushAddr(val,
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tc->getITBPtr()->flushAddr(val,
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EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
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AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
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break;
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break;
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default:
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default:
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@ -36,10 +36,7 @@
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#include "config/alpha_tlaser.hh"
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#include "config/alpha_tlaser.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/isa_traits.hh"
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namespace EV5 {
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namespace AlphaISA {
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//It seems like a safe assumption EV5 only applies to alpha
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using namespace AlphaISA;
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#if ALPHA_TLASER
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#if ALPHA_TLASER
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const uint64_t AsnMask = ULL(0x7f);
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const uint64_t AsnMask = ULL(0x7f);
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@ -120,6 +117,6 @@ inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
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const Addr PalBase = 0x4000;
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const Addr PalBase = 0x4000;
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const Addr PalMax = 0x10000;
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const Addr PalMax = 0x10000;
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/* namespace EV5 */ }
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_EV5_HH__
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#endif // __ARCH_ALPHA_EV5_HH__
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@ -148,8 +148,8 @@ void DtbFault::invoke(ThreadContext * tc)
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// set MM_STAT register flags
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// set MM_STAT register flags
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tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
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tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
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(((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
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(((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11)
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| ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
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| ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6)
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| (flags & 0x3f)));
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| (flags & 0x3f)));
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// set VA_FORM register with faulting formatted address
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// set VA_FORM register with faulting formatted address
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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{
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Fault fault = NoFault; // dummy... this ipr access should not fault
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Fault fault = NoFault; // dummy... this ipr access should not fault
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if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
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if (!AlphaISA::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
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fault = new FloatEnableFault;
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fault = new FloatEnableFault;
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}
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}
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return fault;
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return fault;
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{
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{
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Addr addr = 0;
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Addr addr = 0;
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if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
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if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
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virtPort.write(addr, htog(EV5::Phys2K0Seg(access)));
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virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access)));
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} else
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} else
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panic("could not find m5AlphaAccess\n");
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panic("could not find m5AlphaAccess\n");
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}
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}
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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using namespace std;
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using namespace std;
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using namespace EV5;
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namespace AlphaISA {
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namespace AlphaISA {
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///////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////
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@ -88,8 +88,8 @@ namespace AlphaISA
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// static helper functions... really EV5 VM traits
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// static helper functions... really EV5 VM traits
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static bool validVirtualAddress(Addr vaddr) {
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static bool validVirtualAddress(Addr vaddr) {
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// unimplemented bits must be all 0 or all 1
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// unimplemented bits must be all 0 or all 1
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Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
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Addr unimplBits = vaddr & AlphaISA::VAddrUnImplMask;
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return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
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return (unimplBits == 0) || (unimplBits == AlphaISA::VAddrUnImplMask);
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}
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}
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static Fault checkCacheability(RequestPtr &req, bool itb = false);
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static Fault checkCacheability(RequestPtr &req, bool itb = false);
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Addr paddr = 0;
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
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if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) {
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paddr = vaddr & ~ULL(1);
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paddr = vaddr & ~ULL(1);
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} else {
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} else {
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if (AlphaISA::IsK0Seg(vaddr)) {
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if (AlphaISA::IsK0Seg(vaddr)) {
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/*int
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/*int
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MipsISA::MiscRegFile::getInstAsid()
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MipsISA::MiscRegFile::getInstAsid()
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{
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{
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return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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}
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}
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int
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int
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MipsISA::MiscRegFile::getDataAsid()
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MipsISA::MiscRegFile::getDataAsid()
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{
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{
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return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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}*/
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}*/
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{
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{
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Addr addr = 0;
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Addr addr = 0;
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if (consoleSymtab->findAddress("m5MipsAccess", addr)) {
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if (consoleSymtab->findAddress("m5MipsAccess", addr)) {
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// virtPort.write(addr, htog(EV5::Phys2K0Seg(access)));
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// virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access)));
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} else
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} else
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panic("could not find m5MipsAccess\n");
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panic("could not find m5MipsAccess\n");
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}
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}
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tc->getPhysPort()->getPeerAddressRanges(resp, snoop);
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tc->getPhysPort()->getPeerAddressRanges(resp, snoop);
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for(iter = resp.begin(); iter != resp.end(); iter++)
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for(iter = resp.begin(); iter != resp.end(); iter++)
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{
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{
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if (*iter == (TheISA::K0Seg2Phys(a0) & EV5::PAddrImplMask))
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if (*iter == (TheISA::K0Seg2Phys(a0) & AlphaISA::PAddrImplMask))
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found = true;
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found = true;
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}
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}
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