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ARM: Decode the signed add/subtract and subtract/add instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:06 -05:00
parent 8ba812f1fb
commit 0aff168f1a
1 changed files with 6 additions and 4 deletions
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10
src/arch/arm/isa/formats/data.isa
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@ -236,9 +236,9 @@ def format ArmParallelAddSubtract() {{
case 0x0: case 0x0:
return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x1: case 0x1:
return new WarnUnimplemented("sasx", machInst); return new SasxRegCc(machInst, rd, rn, rm, 0, LSL);
case 0x2: case 0x2:
return new WarnUnimplemented("ssax", machInst); return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL);
case 0x3: case 0x3:
return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x4: case 0x4:
@ -553,9 +553,11 @@ def format Thumb32DataProcReg() {{
return new Sadd16RegCc(machInst, rd, return new Sadd16RegCc(machInst, rd,
rn, rm, 0, LSL); rn, rm, 0, LSL);
case 0x2: case 0x2:
return new WarnUnimplemented("sasx", machInst); return new SasxRegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x6: case 0x6:
return new WarnUnimplemented("ssax", machInst); return new SsaxRegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x5: case 0x5:
return new Ssub16RegCc(machInst, rd, return new Ssub16RegCc(machInst, rd,
rn, rm, 0, LSL); rn, rm, 0, LSL);