CPU: fix sparc_fs booting with SimpleTimingCPU.

--HG--
extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
This commit is contained in:
Ali Saidi 2007-10-01 02:55:27 -04:00
parent 272d867402
commit 0acf891c32
3 changed files with 53 additions and 2 deletions

View file

@ -29,6 +29,7 @@
*/
#include "arch/locked_mem.hh"
#include "arch/mmaped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "cpu/exetrace.hh"
@ -266,7 +267,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
Packet::Broadcast);
pkt->dataDynamic<T>(new T);
if (!dcachePort.sendTiming(pkt)) {
if (req->isMmapedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, nextCycle(curTick + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(pkt)) {
_status = DcacheRetry;
dcache_pkt = pkt;
} else {
@ -375,7 +382,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt->set(data);
if (do_access) {
if (!dcachePort.sendTiming(dcache_pkt)) {
if (req->isMmapedIpr()) {
Tick delay;
dcache_pkt->set(htog(data));
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(dcache_pkt)) {
_status = DcacheRetry;
} else {
_status = DcacheWaitResponse;
@ -551,6 +565,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
}
postExecute();
// @todo remove me after debugging with legion done
if (curStaticInst && (!curStaticInst->isMicroop() ||
curStaticInst->isFirstMicroop()))
instCnt++;
advanceInst(fault);
}
} else {
@ -567,6 +585,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
}
postExecute();
// @todo remove me after debugging with legion done
if (curStaticInst && (!curStaticInst->isMicroop() ||
curStaticInst->isFirstMicroop()))
instCnt++;
advanceInst(fault);
}
@ -730,6 +752,24 @@ TimingSimpleCPU::DcachePort::recvRetry()
}
}
TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
: Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
{
schedule(t);
}
void
TimingSimpleCPU::IprEvent::process()
{
cpu->completeDataAccess(pkt);
}
const char *
TimingSimpleCPU::IprEvent::description()
{
return "Timing Simple CPU Delay IPR event";
}
////////////////////////////////////////////////////////////////////////
//

View file

@ -203,6 +203,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
FetchEvent *fetchEvent;
struct IprEvent : Event {
Packet *pkt;
TimingSimpleCPU *cpu;
IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
virtual void process();
virtual const char *description();
};
void completeDrain();
};

View file

@ -56,6 +56,9 @@ Iob::Iob(const Params *p)
iobJBusAddr = ULL(0x9F00000000);
iobJBusSize = ULL(0x0100000000);
assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
pioDelay = p->pio_latency;
// Get the interrupt controller from the platform
ic = platform->intrctrl;