From 0ac462459522771c7836f5f53e82c6a679c256ca Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Mon, 28 Jul 2014 12:22:00 -0400 Subject: [PATCH] arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2 the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache. --- configs/common/O3_ARM_v7a.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 0202d19e4..5a94438d7 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache): prefetch_on_access = 'true' # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) - + tags = RandomRepl()