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ARM: Implement numcpus bits in L2CTLR register.

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This commit is contained in:
Daniel Johnson 2011-09-13 12:06:13 -05:00
parent 0c29a97ba9
commit 09a6e424ec
3 changed files with 41 additions and 1 deletions
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9
src/arch/arm/isa.cc
View file

@ -227,6 +227,12 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
case MISCREG_FPSCR_EXC: case MISCREG_FPSCR_EXC:
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
case MISCREG_L2CTLR:
// mostly unimplemented, just set NumCPUs field from sim and return
L2CTLR l2ctlr = 0;
// b00:1CPU to b11:4CPUs
l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
return l2ctlr;
} }
return readMiscRegNoEffect(misc_reg); return readMiscRegNoEffect(misc_reg);
} }
@ -537,6 +543,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
// see all of the registers for the copy. // see all of the registers for the copy.
updateRegMap(val); updateRegMap(val);
return; return;
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
miscRegName[misc_reg], uint32_t(val));
} }
} }
setMiscRegNoEffect(misc_reg, newVal); setMiscRegNoEffect(misc_reg, newVal);

14
src/arch/arm/miscregs.cc
View file

@ -382,7 +382,19 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
} }
} }
} else if (opc1 == 1) { } else if (opc1 == 1) {
return MISCREG_L2LATENCY; switch (crm) {
case 0:
switch (opc2) {
case 2: // L2CTLR, L2 Control Register
return MISCREG_L2CTLR;
default:
warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
crn,crm, opc1,opc2);
break;
}
default:
return MISCREG_L2LATENCY;
}
} }
//Reserved for Branch Predictor, Cache and TCM operations //Reserved for Branch Predictor, Cache and TCM operations
break; break;

19
src/arch/arm/miscregs.hh
View file

@ -177,6 +177,7 @@ namespace ArmISA
MISCREG_LOCKFLAG, MISCREG_LOCKFLAG,
MISCREG_LOCKADDR, MISCREG_LOCKADDR,
MISCREG_ID_PFR1, MISCREG_ID_PFR1,
MISCREG_L2CTLR,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_DFR0, MISCREG_ID_DFR0,
@ -238,6 +239,7 @@ namespace ArmISA
"pmuserenr", "pmintenset", "pmintenclr", "pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"cpsr_mode", "lockflag", "lockaddr", "id_pfr1", "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
"l2ctlr",
// Unimplemented below // Unimplemented below
"tcmtr", "tcmtr",
"id_dfr0", "id_afr0", "id_dfr0", "id_afr0",
@ -432,6 +434,23 @@ namespace ArmISA
Bitfield<31,30> or7; Bitfield<31,30> or7;
EndBitUnion(NMRR) EndBitUnion(NMRR)
BitUnion32(L2CTLR)
Bitfield<2,0> sataRAMLatency;
Bitfield<4,3> reserved_4_3;
Bitfield<5> dataRAMSetup;
Bitfield<8,6> tagRAMLatency;
Bitfield<9> tagRAMSetup;
Bitfield<11,10> dataRAMSlice;
Bitfield<12> tagRAMSlice;
Bitfield<20,13> reserved_20_13;
Bitfield<21> eccandParityEnable;
Bitfield<22> reserved_22;
Bitfield<23> interptCtrlPresent;
Bitfield<25,24> numCPUs;
Bitfield<30,26> reserved_30_26;
Bitfield<31> l2rstDISABLE_monitor;
EndBitUnion(L2CTLR)
}; };
#endif // __ARCH_ARM_MISCREGS_HH__ #endif // __ARCH_ARM_MISCREGS_HH__