add an l2 cache option to se example config

configs/common/Options.py:
configs/example/fs.py:
    move l2 cache option to Options.py

--HG--
extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8

configs/common/Options.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -31,6 +31,7 @@ parser.add_option("-d", "--detailed", action="store_true")
 parser.add_option("-t", "--timing", action="store_true")
 parser.add_option("-n", "--num_cpus", type="int", default=1)
 parser.add_option("--caches", action="store_true")
+parser.add_option("--l2cache", action="store_true")
 
 # Run duration options
 parser.add_option("-m", "--maxtick", type="int")

configs/example/fs.py

@@ -51,7 +51,6 @@ parser.add_option("--kernel", action="store", type="string")
 parser.add_option("--script", action="store", type="string")
 
 # Benchmark options
-parser.add_option("--l2cache", action="store_true")
 parser.add_option("--dual", action="store_true",
                   help="Simulate two systems attached with an ethernet link")
 parser.add_option("-b", "--benchmark", action="store", type="string",

configs/example/se.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -104,6 +104,13 @@ for i in xrange(np):
     if options.caches:
         system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                               L1Cache(size = '64kB'))
+    if options.l2cache:
+        system.l2 = L2Cache(size='2MB')
+        system.tol2bus = Bus()
+        system.l2.cpu_side = system.tol2bus.port
+        system.l2.mem_side = system.membus.port
+        system.cpu[i].connectMemPorts(system.tol2bus)
+    else:
         system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process