change how much of the param string is copied into the kenel
Set locked flag if required make SC always return success -- this needs to be fixed at some point fix a couple of things FS executes a bit of console code before dying a horrible death arch/alpha/linux/system.cc: only need to copy the length of the os flags param, not 256 bytes cpu/simple/cpu.cc: Set the physical flag if required Make LL/SC always return success mem/bus.cc: add some dprintfs and change a assert to a panic mem/port.cc: delete the buffer with the [] operator mem/request.hh: add a function to reset a request --HG-- extra : convert_revision : f2b78ddad33c7f6ffe1c48791d86609ff1d10d46
This commit is contained in:
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@ -73,7 +73,7 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p)
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* kernel arguments directly into the kernel's memory.
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* kernel arguments directly into the kernel's memory.
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*/
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*/
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virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
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virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
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CommandLineSize);
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params()->boot_osflags.length()+1);
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/**
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/**
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* find the address of the est_cycle_freq variable and insert it
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* find the address of the est_cycle_freq variable and insert it
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@ -662,6 +662,11 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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if (data_write_req->getFlags() & UNCACHEABLE)
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if (data_write_req->getFlags() & UNCACHEABLE)
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recordEvent("Uncached Write");
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recordEvent("Uncached Write");
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// @todo this is a hack and only works on uniprocessor systems some one else
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// can implement LL/SC.
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if (data_write_req->getFlags() & LOCKED)
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*res = 1;
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// If the write needs to have a fault on the access, consider calling
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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// changeStatus() and changing it to "bad addr write" or something.
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return fault;
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return fault;
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@ -957,11 +962,6 @@ SimpleCPU::tick()
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// Try to fetch an instruction
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// Try to fetch an instruction
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// set up memory request for instruction fetch
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// set up memory request for instruction fetch
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#if FULL_SYSTEM
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#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
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#else
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#define IFETCH_FLAGS(pc) 0
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#endif
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
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cpuXC->readNextPC(),cpuXC->readNextNPC());
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cpuXC->readNextPC(),cpuXC->readNextNPC());
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@ -971,12 +971,14 @@ SimpleCPU::tick()
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ifetch_req->setSize(sizeof(MachInst));
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ifetch_req->setSize(sizeof(MachInst));
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#endif
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#endif
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ifetch_req->reset(true);
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ifetch_req->setVaddr(cpuXC->readPC() & ~3);
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ifetch_req->setVaddr(cpuXC->readPC() & ~3);
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ifetch_req->setTime(curTick);
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ifetch_req->setTime(curTick);
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#if FULL_SYSTEM
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/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
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ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
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IFETCH_FLAGS(xc->regs.pc));
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#else
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*/
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ifetch_req->setFlags(0);
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#endif
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fault = cpuXC->translateInstReq(ifetch_req);
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fault = cpuXC->translateInstReq(ifetch_req);
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12
mem/bus.cc
12
mem/bus.cc
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@ -31,7 +31,8 @@
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*/
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*/
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#include "bus.hh"
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#include "base/trace.hh"
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#include "mem/bus.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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/** Function called by the port when the bus is recieving a Timing
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/** Function called by the port when the bus is recieving a Timing
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@ -57,8 +58,11 @@ Bus::findPort(Addr addr, int id)
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dest_id = portList[i].portId;
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dest_id = portList[i].portId;
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found = true;
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found = true;
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}
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}
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i++;
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}
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}
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assert(dest_id != -1 && "Unable to find destination");
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if (dest_id == -1)
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panic("Unable to find destination for addr: %llx", addr);
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// we shouldn't be sending this back to where it came from
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// we shouldn't be sending this back to where it came from
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assert(dest_id != id);
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assert(dest_id != id);
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@ -99,11 +103,15 @@ Bus::recvStatusChange(Port::Status status, int id)
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assert(snoops.size() == 0);
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assert(snoops.size() == 0);
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// or multiple ranges
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// or multiple ranges
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assert(ranges.size() == 1);
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assert(ranges.size() == 1);
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DevMap dm;
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DevMap dm;
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dm.portId = id;
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dm.portId = id;
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dm.range = ranges.front();
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dm.range = ranges.front();
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DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start,
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dm.range.end, id);
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portList.push_back(dm);
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portList.push_back(dm);
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DPRINTF(MMU, "port list has %d entries\n", portList.size());
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}
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}
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void
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void
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@ -72,5 +72,5 @@ Port::memsetBlob(Addr addr, uint8_t val, int size)
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memset(buf, val, size);
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memset(buf, val, size);
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blobHelper(addr, buf, size, Write);
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blobHelper(addr, buf, size, Write);
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delete buf;
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delete [] buf;
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}
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}
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@ -63,9 +63,13 @@ class Request
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{
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{
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//@todo Make Accesor functions, make these private.
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//@todo Make Accesor functions, make these private.
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public:
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public:
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/** Cunstructor, needs a bool to signify if it is/isn't Cpu Request. */
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/** Constructor, needs a bool to signify if it is/isn't Cpu Request. */
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Request(bool isCpu);
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Request(bool isCpu);
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/** reset the request to it's initial state so it can be reused by the
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* CPU.*/
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void reset(bool isCpu);
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//First non-cpu request fields
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//First non-cpu request fields
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private:
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private:
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/** The physical address of the request. */
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/** The physical address of the request. */
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