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This commit is contained in:
Gabe Black 2011-02-07 19:23:13 -08:00
parent 1b64bfa933
commit 0851580aad
388 changed files with 6117 additions and 2653 deletions
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11
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU

8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 17 2011 16:24:53 M5 compiled Feb 7 2011 01:47:18
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 17 2011 16:40:29 M5 started Feb 7 2011 01:47:50
M5 executing on zizzer M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

31
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 207877 # Simulator instruction rate (inst/s) host_inst_rate 121046 # Simulator instruction rate (inst/s)
host_mem_usage 206352 # Number of bytes of host memory used host_mem_usage 226784 # Number of bytes of host memory used
host_seconds 2720.61 # Real time elapsed on the host host_seconds 4672.20 # Real time elapsed on the host
host_tick_rate 59832123 # Simulator tick rate (ticks/s) host_tick_rate 34840083 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.162780 # Number of seconds simulated sim_seconds 0.162780 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:count 601856963 # Number of instructions committed
system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed.
system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:loads 114514042 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 153965363 # Number of memory references committed system.cpu.commit.COM:refs 153965363 # Number of memory references committed
@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 265 # number of floating regfile reads
system.cpu.fp_regfile_writes 58 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency
@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3177577 #
system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 844691087 # number of integer regfile reads
system.cpu.int_regfile_writes 489153092 # number of integer regfile writes
system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate
system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17165638 # Nu
system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 325559560 # number of cpu cycles simulated system.cpu.numCycles 325559560 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full
@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 115552585 # Nu
system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 958179178 # The number of ROB reads
system.cpu.rob.rob_writes 1334457472 # The number of ROB writes
system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

13
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -57,7 +66,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

6
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Feb 7 2011 01:47:18
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Nov 2 2010 21:31:02 M5 started Feb 7 2011 01:47:37
M5 executing on aus-bc2-b15 M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 6224890 # Simulator instruction rate (inst/s) host_inst_rate 1697811 # Simulator instruction rate (inst/s)
host_mem_usage 232016 # Number of bytes of host memory used host_mem_usage 218112 # Number of bytes of host memory used
host_seconds 96.69 # Real time elapsed on the host host_seconds 354.49 # Real time elapsed on the host
host_tick_rate 3112463113 # Simulator tick rate (ticks/s) host_tick_rate 848911876 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated sim_seconds 0.300931 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 601861917 # number of cpu cycles simulated system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 153970296 # Number of memory references system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

13
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -157,7 +166,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

6
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

10
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Feb 7 2011 01:47:18
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Nov 2 2010 21:44:32 M5 started Feb 7 2011 01:47:36
M5 executing on aus-bc2-b15 M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2723974 # Simulator instruction rate (inst/s) host_inst_rate 591495 # Simulator instruction rate (inst/s)
host_mem_usage 239668 # Number of bytes of host memory used host_mem_usage 225828 # Number of bytes of host memory used
host_seconds 220.95 # Real time elapsed on the host host_seconds 1017.52 # Real time elapsed on the host
host_tick_rate 3465167347 # Simulator tick rate (ticks/s) host_tick_rate 752441266 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.765623 # Number of seconds simulated sim_seconds 0.765623 # Number of seconds simulated
@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 59341 # number of writebacks system.cpu.l2cache.writebacks 59341 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.numCycles 1531246064 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 153970296 # Number of memory references system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

13
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -484,7 +493,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 11 2011 18:16:01 M5 compiled Feb 7 2011 01:56:16
M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 12 2011 02:01:01 M5 started Feb 7 2011 01:59:50
M5 executing on u200439-lin.austin.arm.com M5 executing on burrito
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

30
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 117336 # Simulator instruction rate (inst/s) host_inst_rate 115233 # Simulator instruction rate (inst/s)
host_mem_usage 251760 # Number of bytes of host memory used host_mem_usage 238284 # Number of bytes of host memory used
host_seconds 5118.46 # Real time elapsed on the host host_seconds 5211.87 # Real time elapsed on the host
host_tick_rate 42393313 # Simulator tick rate (ticks/s) host_tick_rate 41633525 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581394 # Number of instructions simulated sim_insts 600581394 # Number of instructions simulated
sim_seconds 0.216988 # Number of seconds simulated sim_seconds 0.216988 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle
system.cpu.commit.COM:count 600581394 # Number of instructions committed system.cpu.commit.COM:count 600581394 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 531746837 # Number of committed integer instructions.
system.cpu.commit.COM:loads 148953025 # Number of loads committed system.cpu.commit.COM:loads 148953025 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 219174038 # Number of memory references committed system.cpu.commit.COM:refs 219174038 # Number of memory references committed
@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency
@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 18357789 #
system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1741733302 # number of integer regfile reads
system.cpu.int_regfile_writes 500762065 # number of integer regfile writes
system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 661113885 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1748261718 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 638555076 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 843800706 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ
@ -470,7 +484,11 @@ system.cpu.memDep0.conflictingLoads 56143840 # Nu
system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 960863166 # number of misc regfile reads
system.cpu.misc_regfile_writes 9367 # number of misc regfile writes
system.cpu.numCycles 433976628 # number of cpu cycles simulated system.cpu.numCycles 433976628 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full
@ -484,10 +502,14 @@ system.cpu.rename.RENAME:RunCycles 140765492 # Nu
system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2146132242 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1130322956 # The number of ROB reads
system.cpu.rob.rob_writes 1461347493 # The number of ROB writes
system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

15
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -52,12 +61,12 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

10
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 19:16:15 M5 started Feb 7 2011 02:00:03
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

26
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2821771 # Simulator instruction rate (inst/s) host_inst_rate 1026292 # Simulator instruction rate (inst/s)
host_mem_usage 253968 # Number of bytes of host memory used host_mem_usage 229344 # Number of bytes of host memory used
host_seconds 212.84 # Real time elapsed on the host host_seconds 585.20 # Real time elapsed on the host
host_tick_rate 1410937507 # Simulator tick rate (ticks/s) host_tick_rate 513165203 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581394 # Number of instructions simulated sim_insts 600581394 # Number of instructions simulated
sim_seconds 0.300302 # Number of seconds simulated sim_seconds 0.300302 # Number of seconds simulated
@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 600604284 # number of cpu cycles simulated system.cpu.numCycles 600604284 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 600604284 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 600581394 # Number of instructions executed system.cpu.num_insts 600581394 # Number of instructions executed
system.cpu.num_refs 219174038 # Number of memory references system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses
system.cpu.num_int_insts 531746837 # number of integer instructions
system.cpu.num_int_register_reads 1690709529 # number of times the integer registers were read
system.cpu.num_int_register_writes 456307392 # number of times the integer registers were written
system.cpu.num_load_insts 148953025 # Number of load instructions
system.cpu.num_mem_refs 219174038 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

15
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -152,12 +161,12 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

4
tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
View file

@ -1,3 +1,7 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Complete acc isn't called on normal stores in O3.
For more information see: http://www.m5sim.org/warn/138d8573
warn: Complete acc isn't called on normal stores in O3.
For more information see: http://www.m5sim.org/warn/138d8573
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

10
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 18:44:50 M5 started Feb 7 2011 01:56:25
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

26
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 652561 # Simulator instruction rate (inst/s) host_inst_rate 452045 # Simulator instruction rate (inst/s)
host_mem_usage 261720 # Number of bytes of host memory used host_mem_usage 237056 # Number of bytes of host memory used
host_seconds 917.34 # Real time elapsed on the host host_seconds 1324.25 # Real time elapsed on the host
host_tick_rate 868554806 # Simulator tick rate (ticks/s) host_tick_rate 601669731 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated sim_insts 598619824 # Number of instructions simulated
sim_seconds 0.796760 # Number of seconds simulated sim_seconds 0.796760 # Number of seconds simulated
@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1593519872 # number of cpu cycles simulated system.cpu.numCycles 1593519872 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1593519872 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_insts 598619824 # Number of instructions executed
system.cpu.num_refs 219174038 # Number of memory references system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses
system.cpu.num_int_insts 531746837 # number of integer instructions
system.cpu.num_int_register_reads 1837343724 # number of times the integer registers were read
system.cpu.num_int_register_writes 456308029 # number of times the integer registers were written
system.cpu.num_load_insts 148953025 # Number of load instructions
system.cpu.num_mem_refs 219174038 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

11
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 17 2011 21:17:52 M5 compiled Feb 7 2011 02:13:30
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 17 2011 21:17:55 M5 started Feb 7 2011 02:13:36
M5 executing on zizzer M5 executing on burrito
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

31
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 144426 # Simulator instruction rate (inst/s) host_inst_rate 165526 # Simulator instruction rate (inst/s)
host_mem_usage 207996 # Number of bytes of host memory used host_mem_usage 228372 # Number of bytes of host memory used
host_seconds 9732.45 # Real time elapsed on the host host_seconds 8491.76 # Real time elapsed on the host
host_tick_rate 61799305 # Simulator tick rate (ticks/s) host_tick_rate 70828550 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated sim_insts 1405604152 # Number of instructions simulated
sim_seconds 0.601459 # Number of seconds simulated sim_seconds 0.601459 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 # Number of instructions committed system.cpu.commit.COM:count 1489523295 # Number of instructions committed
system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569360986 # Number of memory references committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed
@ -160,6 +163,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads
system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency
@ -259,6 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 21427986 #
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads
system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes
system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -350,6 +357,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate
system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ
@ -430,7 +445,11 @@ system.cpu.memDep0.conflictingLoads 406523724 # Nu
system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
system.cpu.numCycles 1202917849 # number of cpu cycles simulated system.cpu.numCycles 1202917849 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
@ -445,10 +464,14 @@ system.cpu.rename.RENAME:RunCycles 329588798 # Nu
system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 2859629611 # The number of ROB reads
system.cpu.rob.rob_writes 3448202738 # The number of ROB writes
system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls system.cpu.workload.PROG:num_syscalls 49 # Number of system calls

13
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -57,7 +66,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Feb 25 2010 03:11:27 M5 compiled Feb 7 2011 02:13:30
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 25 2010 03:19:07 M5 started Feb 7 2011 02:14:57
M5 executing on SC2B0619 M5 executing on burrito
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1748575 # Simulator instruction rate (inst/s) host_inst_rate 1524596 # Simulator instruction rate (inst/s)
host_mem_usage 185740 # Number of bytes of host memory used host_mem_usage 219684 # Number of bytes of host memory used
host_seconds 851.85 # Real time elapsed on the host host_seconds 977.00 # Real time elapsed on the host
host_tick_rate 874289976 # Simulator tick rate (ticks/s) host_tick_rate 762300416 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated sim_seconds 0.744764 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 744764119000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1489528239 # number of cpu cycles simulated system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1489528239 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_insts 1489523295 # Number of instructions executed
system.cpu.num_refs 569365767 # Number of memory references system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

15
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -152,12 +161,12 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

10
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Sep 20 2010 15:04:49 M5 compiled Feb 7 2011 02:13:30
M5 revision 0c4a7d867247 7686 default qtip print-identical tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Sep 20 2010 16:28:00 M5 started Feb 7 2011 02:13:36
M5 executing on phenom M5 executing on burrito
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

26
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1333935 # Simulator instruction rate (inst/s) host_inst_rate 594721 # Simulator instruction rate (inst/s)
host_mem_usage 197236 # Number of bytes of host memory used host_mem_usage 227400 # Number of bytes of host memory used
host_seconds 1116.64 # Real time elapsed on the host host_seconds 2504.58 # Real time elapsed on the host
host_tick_rate 1848636408 # Simulator tick rate (ticks/s) host_tick_rate 824195004 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.064259 # Number of seconds simulated sim_seconds 2.064259 # Number of seconds simulated
@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.l2cache.writebacks 59035 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 4128517334 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_insts 1489523295 # Number of instructions executed
system.cpu.num_refs 569365767 # Number of memory references system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -481,7 +488,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 16:34:44 M5 compiled Feb 7 2011 02:32:07
M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 16:34:46 M5 started Feb 7 2011 02:32:13
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

29
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 136188 # Simulator instruction rate (inst/s) host_inst_rate 168346 # Simulator instruction rate (inst/s)
host_mem_usage 231788 # Number of bytes of host memory used host_mem_usage 232444 # Number of bytes of host memory used
host_seconds 11906.26 # Real time elapsed on the host host_seconds 9631.89 # Real time elapsed on the host
host_tick_rate 64872637 # Simulator tick rate (ticks/s) host_tick_rate 80190939 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493982 # Number of instructions simulated sim_insts 1621493982 # Number of instructions simulated
sim_seconds 0.772390 # Number of seconds simulated sim_seconds 0.772390 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle
system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:count 1621493982 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.COM:loads 419042125 # Number of loads committed system.cpu.commit.COM:loads 419042125 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed
@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency
@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 22026294 #
system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads
system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes
system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued
@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ
@ -420,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 289036318 # Nu
system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads
system.cpu.numCycles 1544781000 # number of cpu cycles simulated system.cpu.numCycles 1544781000 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full
@ -434,10 +451,14 @@ system.cpu.rename.RENAME:RunCycles 968560202 # Nu
system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3357159543 # The number of ROB reads
system.cpu.rob.rob_writes 3732197477 # The number of ROB writes
system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

9
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -54,7 +61,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:38:48
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

26
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1409865 # Simulator instruction rate (inst/s) host_inst_rate 1066510 # Simulator instruction rate (inst/s)
host_mem_usage 219780 # Number of bytes of host memory used host_mem_usage 223440 # Number of bytes of host memory used
host_seconds 1150.11 # Real time elapsed on the host host_seconds 1520.37 # Real time elapsed on the host
host_tick_rate 838177430 # Simulator tick rate (ticks/s) host_tick_rate 634049597 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated sim_insts 1621493983 # Number of instructions simulated
sim_seconds 0.963993 # Number of seconds simulated sim_seconds 0.963993 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 963992704000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_insts 1621493983 # Number of instructions executed
system.cpu.num_refs 607228182 # Number of memory references system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -154,7 +161,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:32:35
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init

26
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1099985 # Simulator instruction rate (inst/s) host_inst_rate 685934 # Simulator instruction rate (inst/s)
host_mem_usage 227480 # Number of bytes of host memory used host_mem_usage 231240 # Number of bytes of host memory used
host_seconds 1474.11 # Real time elapsed on the host host_seconds 2363.92 # Real time elapsed on the host
host_tick_rate 1223290364 # Simulator tick rate (ticks/s) host_tick_rate 762824620 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated sim_insts 1621493983 # Number of instructions simulated
sim_seconds 1.803259 # Number of seconds simulated sim_seconds 1.803259 # Number of seconds simulated
@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.l2cache.writebacks 58007 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_insts 1621493983 # Number of instructions executed
system.cpu.num_refs 607228182 # Number of memory references system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

11
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -1,7 +1,9 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=LinuxAlphaSystem type=LinuxAlphaSystem
@ -19,6 +21,13 @@ readfile=tests/halt.sh
symbolfile= symbolfile=
system_rev=1024 system_rev=1024
system_type=34 system_type=34
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.bridge] [system.bridge]
type=Bridge type=Bridge

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 17 2011 17:11:38 M5 compiled Feb 7 2011 01:46:17
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 17 2011 17:12:29 M5 started Feb 7 2011 01:46:32
M5 executing on zizzer M5 executing on burrito
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux info: kernel located at: /dist/m5/system/binaries/vmlinux

54
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 123407 # Simulator instruction rate (inst/s) host_inst_rate 67358 # Simulator instruction rate (inst/s)
host_mem_usage 293584 # Number of bytes of host memory used host_mem_usage 313516 # Number of bytes of host memory used
host_seconds 461.81 # Real time elapsed on the host host_seconds 846.09 # Real time elapsed on the host
host_tick_rate 4116011383 # Simulator tick rate (ticks/s) host_tick_rate 2246601111 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56990797 # Number of instructions simulated sim_insts 56990797 # Number of instructions simulated
sim_seconds 1.900831 # Number of seconds simulated sim_seconds 1.900831 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu0.commit.COM:committed_per_cycle::min_value 0
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle
system.cpu0.commit.COM:count 49773781 # Number of instructions committed system.cpu0.commit.COM:count 49773781 # Number of instructions committed
system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions.
system.cpu0.commit.COM:function_calls 636046 # Number of function calls committed.
system.cpu0.commit.COM:int_insts 46098576 # Number of committed integer instructions.
system.cpu0.commit.COM:loads 7894849 # Number of loads committed system.cpu0.commit.COM:loads 7894849 # Number of loads committed
system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed
system.cpu0.commit.COM:refs 13318728 # Number of memory references committed system.cpu0.commit.COM:refs 13318728 # Number of memory references committed
@ -248,6 +251,8 @@ system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total)
system.cpu0.fp_regfile_reads 120916 # number of floating regfile reads
system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes
system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency
@ -378,6 +383,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores 419501 #
system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly
system.cpu0.int_regfile_reads 66329266 # number of integer regfile reads
system.cpu0.int_regfile_writes 36276231 # number of integer regfile writes
system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued
@ -469,6 +476,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate
system.cpu0.iq.fp_alu_accesses 260476 # Number of floating point alu accesses
system.cpu0.iq.fp_inst_queue_reads 508189 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_wakeup_accesses 246844 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_writes 251997 # Number of floating instruction queue writes
system.cpu0.iq.int_alu_accesses 50944800 # Number of integer alu accesses
system.cpu0.iq.int_inst_queue_reads 181074941 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_wakeup_accesses 49741828 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.int_inst_queue_writes 60494151 # Number of integer instruction queue writes
system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ
@ -584,7 +599,11 @@ system.cpu0.memDep0.conflictingLoads 2324520 # Nu
system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores. system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit.
system.cpu0.misc_regfile_reads 1626369 # number of misc regfile reads
system.cpu0.misc_regfile_writes 787165 # number of misc regfile writes
system.cpu0.numCycles 112762027 # number of cpu cycles simulated system.cpu0.numCycles 112762027 # number of cpu cycles simulated
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full
@ -598,10 +617,14 @@ system.cpu0.rename.RENAME:RunCycles 11035754 # Nu
system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:fp_rename_lookups 359001 # Number of floating rename lookups
system.cpu0.rename.RENAME:int_rename_lookups 72178524 # Number of integer rename lookups
system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed
system.cpu0.rob.rob_reads 134196739 # The number of ROB reads
system.cpu0.rob.rob_writes 115376344 # The number of ROB writes
system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits
@ -632,6 +655,9 @@ system.cpu1.commit.COM:committed_per_cycle::min_value 0
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle
system.cpu1.commit.COM:count 10605058 # Number of instructions committed system.cpu1.commit.COM:count 10605058 # Number of instructions committed
system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions.
system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed.
system.cpu1.commit.COM:int_insts 9814589 # Number of committed integer instructions.
system.cpu1.commit.COM:loads 1991974 # Number of loads committed system.cpu1.commit.COM:loads 1991974 # Number of loads committed
system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed
system.cpu1.commit.COM:refs 3376359 # Number of memory references committed system.cpu1.commit.COM:refs 3376359 # Number of memory references committed
@ -841,6 +867,8 @@ system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total)
system.cpu1.fp_regfile_reads 63103 # number of floating regfile reads
system.cpu1.fp_regfile_writes 63156 # number of floating regfile writes
system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency
@ -971,6 +999,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores 128329 #
system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly
system.cpu1.int_regfile_reads 13933756 # number of integer regfile reads
system.cpu1.int_regfile_writes 7611585 # number of integer regfile writes
system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued
@ -1062,6 +1092,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate
system.cpu1.iq.fp_alu_accesses 125165 # Number of floating point alu accesses
system.cpu1.iq.fp_inst_queue_reads 243017 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_wakeup_accesses 117535 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_writes 119622 # Number of floating instruction queue writes
system.cpu1.iq.int_alu_accesses 10976050 # Number of integer alu accesses
system.cpu1.iq.int_inst_queue_reads 39966063 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_wakeup_accesses 10617468 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.int_inst_queue_writes 13352810 # Number of integer instruction queue writes
system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ
@ -1166,7 +1204,11 @@ system.cpu1.memDep0.conflictingLoads 496033 # Nu
system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores. system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit.
system.cpu1.misc_regfile_reads 594436 # number of misc regfile reads
system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes
system.cpu1.numCycles 19640104 # number of cpu cycles simulated system.cpu1.numCycles 19640104 # number of cpu cycles simulated
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full
@ -1180,10 +1222,14 @@ system.cpu1.rename.RENAME:RunCycles 2359874 # Nu
system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:fp_rename_lookups 171444 # Number of floating rename lookups
system.cpu1.rename.RENAME:int_rename_lookups 15302029 # Number of integer rename lookups
system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed
system.cpu1.rob.rob_reads 29861070 # The number of ROB reads
system.cpu1.rob.rob_writes 24957765 # The number of ROB writes
system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

11
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -1,7 +1,9 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=LinuxAlphaSystem type=LinuxAlphaSystem
@ -19,6 +21,13 @@ readfile=tests/halt.sh
symbolfile= symbolfile=
system_rev=1024 system_rev=1024
system_type=34 system_type=34
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.bridge] [system.bridge]
type=Bridge type=Bridge

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 17 2011 17:11:38 M5 compiled Feb 7 2011 01:46:17
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 17 2011 17:11:41 M5 started Feb 7 2011 01:46:32
M5 executing on zizzer M5 executing on burrito
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux info: kernel located at: /dist/m5/system/binaries/vmlinux

31
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 145689 # Simulator instruction rate (inst/s) host_inst_rate 66360 # Simulator instruction rate (inst/s)
host_mem_usage 291364 # Number of bytes of host memory used host_mem_usage 311288 # Number of bytes of host memory used
host_seconds 364.14 # Real time elapsed on the host host_seconds 799.45 # Real time elapsed on the host
host_tick_rate 5126322811 # Simulator tick rate (ticks/s) host_tick_rate 2334981918 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53051251 # Number of instructions simulated sim_insts 53051251 # Number of instructions simulated
sim_seconds 1.866703 # Number of seconds simulated sim_seconds 1.866703 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle
system.cpu.commit.COM:count 56244349 # Number of instructions committed system.cpu.commit.COM:count 56244349 # Number of instructions committed
system.cpu.commit.COM:fp_insts 324384 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 744090 # Number of function calls committed.
system.cpu.commit.COM:int_insts 52084301 # Number of committed integer instructions.
system.cpu.commit.COM:loads 9107235 # Number of loads committed system.cpu.commit.COM:loads 9107235 # Number of loads committed
system.cpu.commit.COM:membars 227951 # Number of memory barriers committed system.cpu.commit.COM:membars 227951 # Number of memory barriers committed
system.cpu.commit.COM:refs 15496318 # Number of memory references committed system.cpu.commit.COM:refs 15496318 # Number of memory references committed
@ -246,6 +249,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 164450 # number of floating regfile reads
system.cpu.fp_regfile_writes 166718 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency
@ -376,6 +381,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 554299 #
system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 74886349 # number of integer regfile reads
system.cpu.int_regfile_writes 40928930 # number of integer regfile writes
system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
@ -467,6 +474,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate
system.cpu.iq.fp_alu_accesses 341243 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 667907 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 325691 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 334133 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 57747809 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 205867710 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 56371536 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 69251365 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ
@ -578,7 +593,11 @@ system.cpu.memDep0.conflictingLoads 3018201 # Nu
system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1993439 # number of misc regfile reads
system.cpu.misc_regfile_writes 949389 # number of misc regfile writes
system.cpu.numCycles 125102122 # number of cpu cycles simulated system.cpu.numCycles 125102122 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full
@ -592,10 +611,14 @@ system.cpu.rename.RENAME:RunCycles 12514369 # Nu
system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 474968 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 81738953 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 152916375 # The number of ROB reads
system.cpu.rob.rob_writes 131403689 # The number of ROB writes
system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

15
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -484,9 +493,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

8
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 11 2011 18:16:01 M5 compiled Feb 7 2011 01:56:16
M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 12 2011 03:03:04 M5 started Feb 7 2011 01:58:27
M5 executing on u200439-lin.austin.arm.com M5 executing on burrito
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

31
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 109166 # Simulator instruction rate (inst/s) host_inst_rate 65288 # Simulator instruction rate (inst/s)
host_mem_usage 384348 # Number of bytes of host memory used host_mem_usage 370872 # Number of bytes of host memory used
host_seconds 835.45 # Real time elapsed on the host host_seconds 1396.92 # Real time elapsed on the host
host_tick_rate 67095197 # Simulator tick rate (ticks/s) host_tick_rate 40127232 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.056055 # Number of seconds simulated sim_seconds 0.056055 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:count 91202735 # Number of instructions committed system.cpu.commit.COM:count 91202735 # Number of instructions committed
system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions.
system.cpu.commit.COM:loads 22585492 # Number of loads committed system.cpu.commit.COM:loads 22585492 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 27330336 # Number of memory references committed system.cpu.commit.COM:refs 27330336 # Number of memory references committed
@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 47 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency
@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 788441 #
system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 246289928 # number of integer regfile reads
system.cpu.int_regfile_writes 76222702 # number of integer regfile writes
system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate
system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 100131195 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 311849254 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 96607706 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 112840034 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 436025 # Nu
system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 157552604 # number of misc regfile reads
system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes
system.cpu.numCycles 112109302 # number of cpu cycles simulated system.cpu.numCycles 112109302 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 72730212 # Nu
system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 277458644 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 212048427 # The number of ROB reads
system.cpu.rob.rob_writes 208775903 # The number of ROB writes
system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls system.cpu.workload.PROG:num_syscalls 442 # Number of system calls

17
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -52,14 +61,14 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

10
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 18:40:32 M5 started Feb 7 2011 01:56:24
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2560594 # Simulator instruction rate (inst/s) host_inst_rate 937948 # Simulator instruction rate (inst/s)
host_mem_usage 386656 # Number of bytes of host memory used host_mem_usage 362060 # Number of bytes of host memory used
host_seconds 35.62 # Real time elapsed on the host host_seconds 97.24 # Real time elapsed on the host
host_tick_rate 1522136495 # Simulator tick rate (ticks/s) host_tick_rate 557562760 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.054216 # Number of seconds simulated sim_seconds 0.054216 # Number of seconds simulated
@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 108431099 # number of cpu cycles simulated system.cpu.numCycles 108431099 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 108431099 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 91202735 # Number of instructions executed system.cpu.num_insts 91202735 # Number of instructions executed
system.cpu.num_refs 27330336 # Number of memory references system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses
system.cpu.num_int_insts 72483223 # number of integer instructions
system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read
system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written
system.cpu.num_load_insts 22585492 # Number of load instructions
system.cpu.num_mem_refs 27330336 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

17
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -152,14 +161,14 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

4
tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
View file

@ -1,3 +1,7 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Complete acc isn't called on normal stores in O3.
For more information see: http://www.m5sim.org/warn/138d8573
warn: Complete acc isn't called on normal stores in O3.
For more information see: http://www.m5sim.org/warn/138d8573
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

10
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 18:41:18 M5 started Feb 7 2011 01:56:25
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 587679 # Simulator instruction rate (inst/s) host_inst_rate 419592 # Simulator instruction rate (inst/s)
host_mem_usage 394372 # Number of bytes of host memory used host_mem_usage 369772 # Number of bytes of host memory used
host_seconds 155.15 # Real time elapsed on the host host_seconds 217.30 # Real time elapsed on the host
host_tick_rate 954493550 # Simulator tick rate (ticks/s) host_tick_rate 681491064 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91176087 # Number of instructions simulated sim_insts 91176087 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated sim_seconds 0.148086 # Number of seconds simulated
@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 32 # number of writebacks system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 296172438 # number of cpu cycles simulated system.cpu.numCycles 296172438 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 296172438 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 91176087 # Number of instructions executed system.cpu.num_insts 91176087 # Number of instructions executed
system.cpu.num_refs 27330336 # Number of memory references system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses
system.cpu.num_int_insts 72483223 # number of integer instructions
system.cpu.num_int_register_reads 257112085 # number of times the integer registers were read
system.cpu.num_int_register_writes 72558730 # number of times the integer registers were written
system.cpu.num_load_insts 22585492 # Number of load instructions
system.cpu.num_mem_refs 27330336 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

15
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -57,9 +66,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100 gid=100
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Feb 25 2010 03:11:27 M5 compiled Feb 7 2011 02:13:30
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 25 2010 03:27:41 M5 started Feb 7 2011 02:14:01
M5 executing on SC2B0619 M5 executing on burrito
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1458389 # Simulator instruction rate (inst/s) host_inst_rate 1159873 # Simulator instruction rate (inst/s)
host_mem_usage 317928 # Number of bytes of host memory used host_mem_usage 351876 # Number of bytes of host memory used
host_seconds 167.20 # Real time elapsed on the host host_seconds 210.23 # Real time elapsed on the host
host_tick_rate 730976871 # Simulator tick rate (ticks/s) host_tick_rate 581353978 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated sim_seconds 0.122216 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 122215830000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 244431661 # number of cpu cycles simulated system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 244431661 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_insts 243835278 # Number of instructions executed
system.cpu.num_refs 105711442 # Number of memory references system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451609 # number of times the integer registers were written
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

17
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -152,14 +161,14 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100 gid=100
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

10
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Sep 20 2010 15:04:49 M5 compiled Feb 7 2011 02:13:30
M5 revision 0c4a7d867247 7686 default qtip print-identical tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Sep 20 2010 16:31:43 M5 started Feb 7 2011 02:13:48
M5 executing on phenom M5 executing on burrito
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1229097 # Simulator instruction rate (inst/s) host_inst_rate 483058 # Simulator instruction rate (inst/s)
host_mem_usage 329428 # Number of bytes of host memory used host_mem_usage 359588 # Number of bytes of host memory used
host_seconds 198.39 # Real time elapsed on the host host_seconds 504.77 # Real time elapsed on the host
host_tick_rate 1826897848 # Simulator tick rate (ticks/s) host_tick_rate 718005180 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.362431 # Number of seconds simulated sim_seconds 0.362431 # Number of seconds simulated
@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 40 # number of writebacks system.cpu.l2cache.writebacks 40 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 724861774 # number of cpu cycles simulated system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 724861774 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_insts 243835278 # Number of instructions executed
system.cpu.num_refs 105711442 # Number of memory references system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451608 # number of times the integer registers were written
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -481,7 +488,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 16:34:44 M5 compiled Feb 7 2011 02:32:07
M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 16:34:46 M5 started Feb 7 2011 02:32:24
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

30
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 76828 # Simulator instruction rate (inst/s) host_inst_rate 83481 # Simulator instruction rate (inst/s)
host_mem_usage 366252 # Number of bytes of host memory used host_mem_usage 366872 # Number of bytes of host memory used
host_seconds 3621.00 # Real time elapsed on the host host_seconds 3332.41 # Real time elapsed on the host
host_tick_rate 47136339 # Simulator tick rate (ticks/s) host_tick_rate 51218385 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192519 # Number of instructions simulated sim_insts 278192519 # Number of instructions simulated
sim_seconds 0.170681 # Number of seconds simulated sim_seconds 0.170681 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle
system.cpu.commit.COM:count 278192519 # Number of instructions committed system.cpu.commit.COM:count 278192519 # Number of instructions committed
system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.COM:loads 90779388 # Number of loads committed system.cpu.commit.COM:loads 90779388 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 122219139 # Number of memory references committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed
@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 44 # number of floating regfile reads
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency
@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 9599437 #
system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 754340794 # number of integer regfile reads
system.cpu.int_regfile_writes 286169707 # number of integer regfile writes
system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued
@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate
system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ
@ -419,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 22358679 # Nu
system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads
system.cpu.numCycles 341361263 # number of cpu cycles simulated system.cpu.numCycles 341361263 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full
@ -432,10 +450,14 @@ system.cpu.rename.RENAME:RunCycles 222275258 # Nu
system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 708961934 # The number of ROB reads
system.cpu.rob.rob_writes 799263493 # The number of ROB writes
system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls system.cpu.workload.PROG:num_syscalls 444 # Number of system calls

9
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -54,7 +61,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:32:12
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 938582 # Simulator instruction rate (inst/s) host_inst_rate 722489 # Simulator instruction rate (inst/s)
host_mem_usage 354336 # Number of bytes of host memory used host_mem_usage 358012 # Number of bytes of host memory used
host_seconds 296.40 # Real time elapsed on the host host_seconds 385.05 # Real time elapsed on the host
host_tick_rate 570013222 # Simulator tick rate (ticks/s) host_tick_rate 438776725 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.168950 # Number of seconds simulated sim_seconds 0.168950 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 168950072000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 337900145 # number of cpu cycles simulated system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 337900145 # Number of busy cycles
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_insts 278192520 # Number of instructions executed
system.cpu.num_refs 122219139 # Number of memory references system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -154,7 +161,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:32:12
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 734335 # Simulator instruction rate (inst/s) host_inst_rate 424375 # Simulator instruction rate (inst/s)
host_mem_usage 362052 # Number of bytes of host memory used host_mem_usage 365728 # Number of bytes of host memory used
host_seconds 378.84 # Real time elapsed on the host host_seconds 655.54 # Real time elapsed on the host
host_tick_rate 976703915 # Simulator tick rate (ticks/s) host_tick_rate 564440982 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.370011 # Number of seconds simulated sim_seconds 0.370011 # Number of seconds simulated
@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.l2cache.writebacks 29460 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 740021680 # Number of busy cycles
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_insts 278192520 # Number of instructions executed
system.cpu.num_refs 122219139 # Number of memory references system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

15
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -484,9 +493,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

8
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 11 2011 18:16:01 M5 compiled Feb 7 2011 01:56:16
M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 12 2011 03:20:30 M5 started Feb 7 2011 01:56:25
M5 executing on u200439-lin.austin.arm.com M5 executing on burrito
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

30
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 95936 # Simulator instruction rate (inst/s) host_inst_rate 89247 # Simulator instruction rate (inst/s)
host_mem_usage 255716 # Number of bytes of host memory used host_mem_usage 242220 # Number of bytes of host memory used
host_seconds 5851.87 # Real time elapsed on the host host_seconds 6290.45 # Real time elapsed on the host
host_tick_rate 62464794 # Simulator tick rate (ticks/s) host_tick_rate 58109668 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 561403855 # Number of instructions simulated sim_insts 561403855 # Number of instructions simulated
sim_seconds 0.365536 # Number of seconds simulated sim_seconds 0.365536 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle
system.cpu.commit.COM:count 561403855 # Number of instructions committed system.cpu.commit.COM:count 561403855 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 464140463 # Number of committed integer instructions.
system.cpu.commit.COM:loads 128127024 # Number of loads committed system.cpu.commit.COM:loads 128127024 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 184987501 # Number of memory references committed system.cpu.commit.COM:refs 184987501 # Number of memory references committed
@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency
@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 83223254 #
system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1624866525 # number of integer regfile reads
system.cpu.int_regfile_writes 504061562 # number of integer regfile writes
system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate
system.cpu.iq.fp_alu_accesses 140 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 652 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 771704903 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 2266614625 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 674936607 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 1350317509 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ
@ -465,7 +479,11 @@ system.cpu.memDep0.conflictingLoads 60170710 # Nu
system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1169165868 # number of misc regfile reads
system.cpu.misc_regfile_writes 344748 # number of misc regfile writes
system.cpu.numCycles 731071595 # number of cpu cycles simulated system.cpu.numCycles 731071595 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full
@ -479,10 +497,14 @@ system.cpu.rename.RENAME:RunCycles 326862324 # Nu
system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 2110 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2644674034 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1617861624 # The number of ROB reads
system.cpu.rob.rob_writes 1988299741 # The number of ROB writes
system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls system.cpu.workload.PROG:num_syscalls 548 # Number of system calls

17
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -52,14 +61,14 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=parser 2.1.dict -batch cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

10
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 18:37:50 M5 started Feb 7 2011 01:56:25
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2845430 # Simulator instruction rate (inst/s) host_inst_rate 1052675 # Simulator instruction rate (inst/s)
host_mem_usage 257528 # Number of bytes of host memory used host_mem_usage 232888 # Number of bytes of host memory used
host_seconds 197.30 # Real time elapsed on the host host_seconds 533.31 # Real time elapsed on the host
host_tick_rate 1448130657 # Simulator tick rate (ticks/s) host_tick_rate 535740490 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 561403855 # Number of instructions simulated sim_insts 561403855 # Number of instructions simulated
sim_seconds 0.285717 # Number of seconds simulated sim_seconds 0.285717 # Number of seconds simulated
@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 571433624 # number of cpu cycles simulated system.cpu.numCycles 571433624 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 571433624 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 561403855 # Number of instructions executed system.cpu.num_insts 561403855 # Number of instructions executed
system.cpu.num_refs 184987503 # Number of memory references system.cpu.num_int_alu_accesses 464140465 # Number of integer alu accesses
system.cpu.num_int_insts 464140465 # number of integer instructions
system.cpu.num_int_register_reads 1370673061 # number of times the integer registers were read
system.cpu.num_int_register_writes 415936275 # number of times the integer registers were written
system.cpu.num_load_insts 128127024 # Number of load instructions
system.cpu.num_mem_refs 184987503 # number of memory refs
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

17
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -152,14 +161,14 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=parser 2.1.dict -batch cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100 gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

2
tests/long/20.parser/ref/arm/linux/simple-timing/simerr
View file

@ -1,3 +1,5 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Complete acc isn't called on normal stores in O3.
For more information see: http://www.m5sim.org/warn/138d8573
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

10
tests/long/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 11 2010 18:37:23 M5 compiled Feb 7 2011 01:56:16
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Oct 11 2010 19:30:07 M5 started Feb 7 2011 02:00:20
M5 executing on aus-bc3-b4 M5 executing on burrito
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 698342 # Simulator instruction rate (inst/s) host_inst_rate 427899 # Simulator instruction rate (inst/s)
host_mem_usage 265248 # Number of bytes of host memory used host_mem_usage 240600 # Number of bytes of host memory used
host_seconds 801.14 # Real time elapsed on the host host_seconds 1307.48 # Real time elapsed on the host
host_tick_rate 898558125 # Simulator tick rate (ticks/s) host_tick_rate 550579326 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 559470527 # Number of instructions simulated sim_insts 559470527 # Number of instructions simulated
sim_seconds 0.719872 # Number of seconds simulated sim_seconds 0.719872 # Number of seconds simulated
@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 510281834000 # Cy
system.cpu.l2cache.writebacks 172310 # number of writebacks system.cpu.l2cache.writebacks 172310 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1439744848 # number of cpu cycles simulated system.cpu.numCycles 1439744848 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1439744848 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 559470527 # Number of instructions executed system.cpu.num_insts 559470527 # Number of instructions executed
system.cpu.num_refs 184987503 # Number of memory references system.cpu.num_int_alu_accesses 464140465 # Number of integer alu accesses
system.cpu.num_int_insts 464140465 # number of integer instructions
system.cpu.num_int_register_reads 1497198689 # number of times the integer registers were read
system.cpu.num_int_register_writes 415939738 # number of times the integer registers were written
system.cpu.num_load_insts 128127024 # Number of load instructions
system.cpu.num_mem_refs 184987503 # number of memory refs
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
@ -481,7 +488,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=parser 2.1.dict -batch cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 16:34:44 M5 compiled Feb 7 2011 02:32:07
M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 16:34:46 M5 started Feb 7 2011 02:32:13
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

29
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 123365 # Simulator instruction rate (inst/s) host_inst_rate 160923 # Simulator instruction rate (inst/s)
host_mem_usage 239740 # Number of bytes of host memory used host_mem_usage 240360 # Number of bytes of host memory used
host_seconds 12393.99 # Real time elapsed on the host host_seconds 9501.35 # Real time elapsed on the host
host_tick_rate 65919204 # Simulator tick rate (ticks/s) host_tick_rate 85987979 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988756 # Number of instructions simulated sim_insts 1528988756 # Number of instructions simulated
sim_seconds 0.817002 # Number of seconds simulated sim_seconds 0.817002 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle
system.cpu.commit.COM:count 1528988756 # Number of instructions committed system.cpu.commit.COM:count 1528988756 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.COM:loads 384102160 # Number of loads committed system.cpu.commit.COM:loads 384102160 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 533262345 # Number of memory references committed system.cpu.commit.COM:refs 533262345 # Number of memory references committed
@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 10 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency
@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 44929168 #
system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads
system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes
system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued
@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate
system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ
@ -430,7 +444,10 @@ system.cpu.memDep0.conflictingLoads 151128770 # Nu
system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads
system.cpu.numCycles 1634004079 # number of cpu cycles simulated system.cpu.numCycles 1634004079 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full
@ -444,10 +461,14 @@ system.cpu.rename.RENAME:RunCycles 1095363349 # Nu
system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3532180532 # The number of ROB reads
system.cpu.rob.rob_writes 4048956705 # The number of ROB writes
system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls system.cpu.workload.PROG:num_syscalls 551 # Number of system calls

9
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -54,7 +61,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=parser 2.1.dict -batch cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:32:12
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1495739 # Simulator instruction rate (inst/s) host_inst_rate 904614 # Simulator instruction rate (inst/s)
host_mem_usage 223620 # Number of bytes of host memory used host_mem_usage 227300 # Number of bytes of host memory used
host_seconds 1022.23 # Real time elapsed on the host host_seconds 1690.21 # Real time elapsed on the host
host_tick_rate 865978759 # Simulator tick rate (ticks/s) host_tick_rate 523739013 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated sim_insts 1528988757 # Number of instructions simulated
sim_seconds 0.885229 # Number of seconds simulated sim_seconds 0.885229 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 885229360000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1770458721 # number of cpu cycles simulated system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_insts 1528988757 # Number of instructions executed
system.cpu.num_refs 533262345 # Number of memory references system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

9
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -10,6 +10,13 @@ type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -154,7 +161,7 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=parser 2.1.dict -batch cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr

8
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 31 2011 14:03:49 M5 compiled Feb 7 2011 02:32:07
M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 31 2011 14:03:51 M5 started Feb 7 2011 02:36:47
M5 executing on burrito M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1108188 # Simulator instruction rate (inst/s) host_inst_rate 738382 # Simulator instruction rate (inst/s)
host_mem_usage 231336 # Number of bytes of host memory used host_mem_usage 235020 # Number of bytes of host memory used
host_seconds 1379.72 # Real time elapsed on the host host_seconds 2070.73 # Real time elapsed on the host
host_tick_rate 1202222105 # Simulator tick rate (ticks/s) host_tick_rate 801036637 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated sim_insts 1528988757 # Number of instructions simulated
sim_seconds 1.658730 # Number of seconds simulated sim_seconds 1.658730 # Number of seconds simulated
@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 896565143000 # Cy
system.cpu.l2cache.writebacks 411709 # number of writebacks system.cpu.l2cache.writebacks 411709 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3317459208 # number of cpu cycles simulated system.cpu.numCycles 3317459208 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_insts 1528988757 # Number of instructions executed
system.cpu.num_refs 533262345 # Number of memory references system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU

8
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jan 17 2011 16:24:53 M5 compiled Feb 7 2011 01:47:18
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Jan 17 2011 16:25:09 M5 started Feb 7 2011 01:47:47
M5 executing on zizzer M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

31
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 178067 # Simulator instruction rate (inst/s) host_inst_rate 86954 # Simulator instruction rate (inst/s)
host_mem_usage 212832 # Number of bytes of host memory used host_mem_usage 233264 # Number of bytes of host memory used
host_seconds 2109.17 # Real time elapsed on the host host_seconds 4319.23 # Real time elapsed on the host
host_tick_rate 64635199 # Simulator tick rate (ticks/s) host_tick_rate 31562755 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.136327 # Number of seconds simulated sim_seconds 0.136327 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle
system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed.
system.cpu.commit.COM:int_insts 316365851 # Number of committed integer instructions.
system.cpu.commit.COM:loads 94754489 # Number of loads committed system.cpu.commit.COM:loads 94754489 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 168275218 # Number of memory references committed system.cpu.commit.COM:refs 168275218 # Number of memory references committed
@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 161565122 # number of floating regfile reads
system.cpu.fp_regfile_writes 106206809 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency
@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 19394112 #
system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 421360455 # number of integer regfile reads
system.cpu.int_regfile_writes 182139619 # number of integer regfile writes
system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate
system.cpu.iq.fp_alu_accesses 175992487 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 346671239 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 165916628 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 231922736 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 262987844 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 796105773 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 251613948 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 330463092 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 71937561 # Nu
system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 272653822 # number of cpu cycles simulated system.cpu.numCycles 272653822 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full
@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 96677987 # Nu
system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 326649614 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 361910200 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 740781417 # The number of ROB reads
system.cpu.rob.rob_writes 1009223784 # The number of ROB writes
system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls

13
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
@ -57,7 +66,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

6
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
getting pixel output filename pixels_out.cook getting pixel output filename pixels_out.cook
opening control file chair.control.cook opening control file chair.control.cook
opening camera file chair.camera opening camera file chair.camera

10
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Feb 7 2011 01:47:18
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Nov 2 2010 21:31:02 M5 started Feb 7 2011 01:47:38
M5 executing on aus-bc2-b15 M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 4732897 # Simulator instruction rate (inst/s) host_inst_rate 1382202 # Simulator instruction rate (inst/s)
host_mem_usage 238480 # Number of bytes of host memory used host_mem_usage 224632 # Number of bytes of host memory used
host_seconds 84.23 # Real time elapsed on the host host_seconds 288.43 # Real time elapsed on the host
host_tick_rate 2366444186 # Simulator tick rate (ticks/s) host_tick_rate 691100750 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated sim_seconds 0.199332 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 398664824 # number of cpu cycles simulated system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 398664824 # Number of busy cycles
system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 398664595 # Number of instructions executed system.cpu.num_insts 398664595 # Number of instructions executed
system.cpu.num_refs 168275274 # Number of memory references system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_int_insts 316365907 # number of integer instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

13
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root] [root]
type=Root type=Root
children=system children=system
dummy=0 time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system] [system]
type=System type=System
children=cpu membus physmem children=cpu membus physmem
mem_mode=atomic mem_mode=atomic
physmem=system.physmem physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
@ -157,7 +166,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

6
tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6 For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
getting pixel output filename pixels_out.cook getting pixel output filename pixels_out.cook
opening control file chair.control.cook opening control file chair.control.cook
opening camera file chair.camera opening camera file chair.camera

10
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Nov 2 2010 21:30:55 M5 compiled Feb 7 2011 01:47:18
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Nov 2 2010 21:41:16 M5 started Feb 7 2011 01:47:38
M5 executing on aus-bc2-b15 M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

26
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2252516 # Simulator instruction rate (inst/s) host_inst_rate 531142 # Simulator instruction rate (inst/s)
host_mem_usage 246196 # Number of bytes of host memory used host_mem_usage 232344 # Number of bytes of host memory used
host_seconds 176.99 # Real time elapsed on the host host_seconds 750.58 # Real time elapsed on the host
host_tick_rate 3205571054 # Simulator tick rate (ticks/s) host_tick_rate 755872580 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567343 # Number of seconds simulated sim_seconds 0.567343 # Number of seconds simulated
@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1134686340 # number of cpu cycles simulated system.cpu.numCycles 1134686340 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_insts 398664609 # Number of instructions executed
system.cpu.num_refs 168275276 # Number of memory references system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_int_insts 316365921 # number of integer instructions
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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