config: Add a system clock command-line option

This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
This commit is contained in:
Akash Bagdia 2013-06-27 05:49:49 -04:00
parent 4459b30525
commit 076d04a653
33 changed files with 40 additions and 8 deletions

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@ -78,6 +78,10 @@ def addCommonOptions(parser):
parser.add_option("--simpoint-interval", type="int", default=10000000, parser.add_option("--simpoint-interval", type="int", default=10000000,
help="SimPoint interval in num of instructions") help="SimPoint interval in num of instructions")
parser.add_option("--clock", action="store", type="string", default='2GHz') parser.add_option("--clock", action="store", type="string", default='2GHz')
parser.add_option("--sys-clock", action="store", type="string",
default='1GHz',
help = """Top-level clock for blocks running at system
speed""")
parser.add_option("--cpu-clock", action="store", type="string", parser.add_option("--cpu-clock", action="store", type="string",
default='2GHz', default='2GHz',
help="Clock for blocks running at CPU speed") help="Clock for blocks running at CPU speed")

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@ -120,6 +120,8 @@ elif buildEnv['TARGET_ISA'] == "arm":
else: else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
test_sys.clock = options.sys_clock
if options.kernel is not None: if options.kernel is not None:
test_sys.kernel = binary(options.kernel) test_sys.kernel = binary(options.kernel)
@ -172,6 +174,8 @@ if len(bm) == 2:
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
DriveMemClass, bm[1]) DriveMemClass, bm[1])
drive_sys.clock = options.sys_clock
drive_sys.cpu = DriveCPUClass(cpu_id=0) drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.createThreads() drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController() drive_sys.cpu.createInterruptController()

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@ -144,6 +144,7 @@ for scale in treespec[:-2]:
system = System(funcmem = SimpleMemory(in_addr_map = False), system = System(funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(), funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns")) physmem = SimpleMemory(latency = "100ns"))
system.clock = options.sys_clock
def make_level(spec, prototypes, attach_obj, attach_port): def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0] fanout = spec[0]

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@ -93,7 +93,7 @@ else:
# M5 memory size == Ruby memory size checks # M5 memory size == Ruby memory size checks
# #
system = System(physmem = SimpleMemory()) system = System(physmem = SimpleMemory())
system.clock = options.sys_clock
# #
# Create the ruby random tester # Create the ruby random tester
# #

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@ -93,6 +93,8 @@ elif buildEnv['TARGET_ISA'] == "x86":
else: else:
fatal("incapable of building non-alpha or non-x86 full system!") fatal("incapable of building non-alpha or non-x86 full system!")
system.clock = options.sys_clock
if options.kernel is not None: if options.kernel is not None:
system.kernel = binary(options.kernel) system.kernel = binary(options.kernel)

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@ -108,6 +108,7 @@ system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False), funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(), funcbus = NoncoherentBus(),
physmem = SimpleMemory()) physmem = SimpleMemory())
system.clock = options.sys_clock
if options.num_dmas > 0: if options.num_dmas > 0:
dmas = [ MemTest(atomic = False, dmas = [ MemTest(atomic = False,

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@ -105,6 +105,7 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
# create the desired simulated system # create the desired simulated system
system = System(cpu = cpus, system = System(cpu = cpus,
physmem = SimpleMemory()) physmem = SimpleMemory())
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

View file

@ -98,6 +98,7 @@ tester = RubyTester(check_flush = check_flush,
# M5 memory size == Ruby memory size checks # M5 memory size == Ruby memory size checks
# #
system = System(tester = tester, physmem = SimpleMemory()) system = System(tester = tester, physmem = SimpleMemory())
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

View file

@ -160,6 +160,7 @@ np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange("512MB")), physmem = MemClass(range=AddrRange("512MB")),
mem_mode = test_mem_mode) mem_mode = test_mem_mode)
system.clock = options.sys_clock
# Sanity check # Sanity check
if options.fastmem: if options.fastmem:

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@ -214,6 +214,7 @@ else:
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus(clock = busFrequency)) membus = CoherentBus(clock = busFrequency))
system.clock = '1GHz'
system.toL2bus = CoherentBus(clock = busFrequency) system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8) system.l2 = L2(size = options.l2size, assoc = 8)

View file

@ -199,6 +199,7 @@ else:
# ---------------------- # ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(), system = System(cpu = cpus, physmem = SimpleMemory(),
membus = CoherentBus(clock = busFrequency)) membus = CoherentBus(clock = busFrequency))
system.clock = '1GHz'
system.toL2bus = CoherentBus(clock = busFrequency) system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8) system.l2 = L2(size = options.l2size, assoc = 8)

View file

@ -43,12 +43,6 @@ class System(MemObject):
cxx_header = "sim/system.hh" cxx_header = "sim/system.hh"
system_port = MasterPort("System port") system_port = MasterPort("System port")
# Override the clock from the ClockedObject which looks at the
# parent clock by default. The 1 GHz default system clock serves
# as a start for the modules that rely on the parent to provide
# the clock.
clock = '1GHz'
@classmethod @classmethod
def export_method_cxx_predecls(cls, code): def export_method_cxx_predecls(cls, code):
code('#include "sim/system.hh"') code('#include "sim/system.hh"')

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@ -131,6 +131,7 @@ class BaseSystem(object):
Arguments: Arguments:
system -- System to initialize. system -- System to initialize.
""" """
system.clock = '1GHz'
system.cpu = self.create_cpus() system.cpu = self.create_cpus()
if _have_kvm_support and \ if _have_kvm_support and \

View file

@ -42,6 +42,7 @@ system = System(cpu = cpu,
physmem = DDR3_1600_x64(), physmem = DDR3_1600_x64(),
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller # create the interrupt controller

View file

@ -81,6 +81,7 @@ system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False), funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True), physmem = SimpleMemory(null = True),
funcbus = NoncoherentBus()) funcbus = NoncoherentBus())
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

View file

@ -40,6 +40,7 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(), funcbus = NoncoherentBus(),
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus(width=16)) membus = CoherentBus(width=16))
system.clock = '1GHz'
# l2cache & bus # l2cache & bus
system.toL2Bus = CoherentBus(clock="2GHz", width=16) system.toL2Bus = CoherentBus(clock="2GHz", width=16)

View file

@ -55,6 +55,7 @@ system = System(cpu = cpu,
physmem = DDR3_1600_x64(), physmem = DDR3_1600_x64(),
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)

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@ -40,6 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated # system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
for cpu in cpus: for cpu in cpus:
# create the interrupt controller # create the interrupt controller

View file

@ -39,6 +39,7 @@ system = System(cpu = cpus,
physmem = DDR3_1600_x64(), physmem = DDR3_1600_x64(),
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
# l2cache & bus # l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz') system.toL2Bus = CoherentBus(clock = '2GHz')

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@ -42,6 +42,7 @@ system = System(cpu = cpu,
physmem = ruby_memory, physmem = ruby_memory,
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller # create the interrupt controller
cpu.createInterruptController() cpu.createInterruptController()

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@ -44,6 +44,7 @@ system = System(cpu = cpu,
physmem = DDR3_1600_x64(), physmem = DDR3_1600_x64(),
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller # create the interrupt controller

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@ -78,6 +78,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
wakeup_frequency = 10, num_cpus = options.num_cpus) wakeup_frequency = 10, num_cpus = options.num_cpus)
system = System(tester = tester, physmem = SimpleMemory(null = True)) system = System(tester = tester, physmem = SimpleMemory(null = True))
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

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@ -41,6 +41,7 @@ from m5.objects import *
system = System(cpu = AtomicSimpleCPU(cpu_id=0), system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus()) membus = CoherentBus())
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
system.cpu.addCheckerCpu() system.cpu.addCheckerCpu()

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@ -39,6 +39,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated # system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus()) system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
system.clock = '1GHz'
# add L1 caches # add L1 caches
for cpu in cpus: for cpu in cpus:

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@ -38,7 +38,7 @@ cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
system = System(cpu = cpus, system = System(cpu = cpus,
physmem = SimpleMemory(range = AddrRange('1024MB')), physmem = SimpleMemory(range = AddrRange('1024MB')),
membus = CoherentBus()) membus = CoherentBus())
system.clock = '1GHz'
# l2cache & bus # l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz') system.toL2Bus = CoherentBus(clock = '2GHz')
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)

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@ -32,6 +32,7 @@ from m5.objects import *
system = System(cpu = AtomicSimpleCPU(cpu_id=0), system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus()) membus = CoherentBus())
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller # create the interrupt controller

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@ -72,6 +72,7 @@ options.num_cpus = nb_cores
# system simulated # system simulated
system = System(cpu = cpus, physmem = SimpleMemory()) system = System(cpu = cpus, physmem = SimpleMemory())
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

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@ -36,6 +36,7 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated # system simulated
system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
system.clock = '1GHz'
# l2cache & bus # l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz') system.toL2Bus = CoherentBus(clock = '2GHz')

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@ -68,6 +68,7 @@ options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0) cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu = cpu, physmem = SimpleMemory(null = True)) system = System(cpu = cpu, physmem = SimpleMemory(null = True))
system.clock = options.sys_clock
Ruby.create_system(options, system) Ruby.create_system(options, system)

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@ -39,6 +39,7 @@ system = System(cpu = cpu,
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus(), membus = CoherentBus(),
mem_mode = "timing") mem_mode = "timing")
system.clock = '1GHz'
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller # create the interrupt controller

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@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
# system simulated # system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(), system = System(cpu = cpu, physmem = DDR3_1600_x64(),
membus = NoncoherentBus(width = 16)) membus = NoncoherentBus(width = 16))
system.clock = '1GHz'
# add a communication monitor # add a communication monitor
system.monitor = CommMonitor() system.monitor = CommMonitor()

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@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
# system simulated # system simulated
system = System(cpu = cpu, physmem = SimpleMemory(), system = System(cpu = cpu, physmem = SimpleMemory(),
membus = NoncoherentBus(width = 16)) membus = NoncoherentBus(width = 16))
system.clock = '1GHz'
# add a communication monitor, and also trace all the packets # add a communication monitor, and also trace all the packets
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")

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@ -34,6 +34,7 @@ from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-stream-client.rcS')) SysConfig('netperf-stream-client.rcS'))
test_sys.clock = '1GHz'
test_sys.cpu = AtomicSimpleCPU(cpu_id=0) test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller # create the interrupt controller
test_sys.cpu.createInterruptController() test_sys.cpu.createInterruptController()
@ -48,6 +49,7 @@ test_sys.iobridge.master = test_sys.membus.slave
drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-server.rcS')) SysConfig('netperf-server.rcS'))
drive_sys.clock = '1GHz'
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller # create the interrupt controller
drive_sys.cpu.createInterruptController() drive_sys.cpu.createInterruptController()