config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign clocks to the system during instantiation. As part of this change, the default clock in the System class is removed and whenever a system is instantiated a system clock value must be set. A default value is provided for the command-line option. The configs and tests are updated accordingly.
This commit is contained in:
parent
4459b30525
commit
076d04a653
33 changed files with 40 additions and 8 deletions
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@ -78,6 +78,10 @@ def addCommonOptions(parser):
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parser.add_option("--simpoint-interval", type="int", default=10000000,
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parser.add_option("--simpoint-interval", type="int", default=10000000,
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help="SimPoint interval in num of instructions")
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help="SimPoint interval in num of instructions")
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parser.add_option("--clock", action="store", type="string", default='2GHz')
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parser.add_option("--clock", action="store", type="string", default='2GHz')
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parser.add_option("--sys-clock", action="store", type="string",
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default='1GHz',
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help = """Top-level clock for blocks running at system
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speed""")
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parser.add_option("--cpu-clock", action="store", type="string",
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parser.add_option("--cpu-clock", action="store", type="string",
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default='2GHz',
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default='2GHz',
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help="Clock for blocks running at CPU speed")
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help="Clock for blocks running at CPU speed")
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@ -120,6 +120,8 @@ elif buildEnv['TARGET_ISA'] == "arm":
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else:
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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test_sys.clock = options.sys_clock
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if options.kernel is not None:
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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test_sys.kernel = binary(options.kernel)
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@ -172,6 +174,8 @@ if len(bm) == 2:
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drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
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drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
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DriveMemClass, bm[1])
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DriveMemClass, bm[1])
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drive_sys.clock = options.sys_clock
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.createThreads()
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drive_sys.cpu.createThreads()
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drive_sys.cpu.createInterruptController()
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drive_sys.cpu.createInterruptController()
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@ -144,6 +144,7 @@ for scale in treespec[:-2]:
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system = System(funcmem = SimpleMemory(in_addr_map = False),
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system = System(funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory(latency = "100ns"))
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physmem = SimpleMemory(latency = "100ns"))
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system.clock = options.sys_clock
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def make_level(spec, prototypes, attach_obj, attach_port):
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def make_level(spec, prototypes, attach_obj, attach_port):
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fanout = spec[0]
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fanout = spec[0]
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@ -93,7 +93,7 @@ else:
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# M5 memory size == Ruby memory size checks
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# M5 memory size == Ruby memory size checks
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#
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#
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system = System(physmem = SimpleMemory())
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system = System(physmem = SimpleMemory())
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system.clock = options.sys_clock
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#
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#
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# Create the ruby random tester
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# Create the ruby random tester
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#
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#
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@ -93,6 +93,8 @@ elif buildEnv['TARGET_ISA'] == "x86":
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else:
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else:
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fatal("incapable of building non-alpha or non-x86 full system!")
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fatal("incapable of building non-alpha or non-x86 full system!")
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system.clock = options.sys_clock
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if options.kernel is not None:
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if options.kernel is not None:
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system.kernel = binary(options.kernel)
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system.kernel = binary(options.kernel)
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@ -108,6 +108,7 @@ system = System(cpu = cpus,
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funcmem = SimpleMemory(in_addr_map = False),
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funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory())
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physmem = SimpleMemory())
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system.clock = options.sys_clock
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if options.num_dmas > 0:
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if options.num_dmas > 0:
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dmas = [ MemTest(atomic = False,
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dmas = [ MemTest(atomic = False,
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@ -105,6 +105,7 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
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# create the desired simulated system
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# create the desired simulated system
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system = System(cpu = cpus,
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system = System(cpu = cpus,
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physmem = SimpleMemory())
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physmem = SimpleMemory())
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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@ -98,6 +98,7 @@ tester = RubyTester(check_flush = check_flush,
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# M5 memory size == Ruby memory size checks
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# M5 memory size == Ruby memory size checks
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#
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#
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system = System(tester = tester, physmem = SimpleMemory())
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system = System(tester = tester, physmem = SimpleMemory())
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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@ -160,6 +160,7 @@ np = options.num_cpus
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system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
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system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
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physmem = MemClass(range=AddrRange("512MB")),
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physmem = MemClass(range=AddrRange("512MB")),
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mem_mode = test_mem_mode)
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mem_mode = test_mem_mode)
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system.clock = options.sys_clock
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# Sanity check
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# Sanity check
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if options.fastmem:
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if options.fastmem:
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@ -214,6 +214,7 @@ else:
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system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
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system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
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physmem = SimpleMemory(),
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physmem = SimpleMemory(),
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membus = CoherentBus(clock = busFrequency))
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membus = CoherentBus(clock = busFrequency))
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system.clock = '1GHz'
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system.toL2bus = CoherentBus(clock = busFrequency)
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system.toL2bus = CoherentBus(clock = busFrequency)
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system.l2 = L2(size = options.l2size, assoc = 8)
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system.l2 = L2(size = options.l2size, assoc = 8)
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@ -199,6 +199,7 @@ else:
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# ----------------------
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# ----------------------
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system = System(cpu = cpus, physmem = SimpleMemory(),
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system = System(cpu = cpus, physmem = SimpleMemory(),
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membus = CoherentBus(clock = busFrequency))
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membus = CoherentBus(clock = busFrequency))
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system.clock = '1GHz'
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system.toL2bus = CoherentBus(clock = busFrequency)
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system.toL2bus = CoherentBus(clock = busFrequency)
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system.l2 = L2(size = options.l2size, assoc = 8)
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system.l2 = L2(size = options.l2size, assoc = 8)
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@ -43,12 +43,6 @@ class System(MemObject):
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cxx_header = "sim/system.hh"
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cxx_header = "sim/system.hh"
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system_port = MasterPort("System port")
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system_port = MasterPort("System port")
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# Override the clock from the ClockedObject which looks at the
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# parent clock by default. The 1 GHz default system clock serves
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# as a start for the modules that rely on the parent to provide
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# the clock.
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clock = '1GHz'
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@classmethod
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@classmethod
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def export_method_cxx_predecls(cls, code):
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def export_method_cxx_predecls(cls, code):
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code('#include "sim/system.hh"')
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code('#include "sim/system.hh"')
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@ -131,6 +131,7 @@ class BaseSystem(object):
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Arguments:
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Arguments:
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system -- System to initialize.
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system -- System to initialize.
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"""
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"""
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system.clock = '1GHz'
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system.cpu = self.create_cpus()
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system.cpu = self.create_cpus()
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if _have_kvm_support and \
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if _have_kvm_support and \
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@ -42,6 +42,7 @@ system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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# create the interrupt controller
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# create the interrupt controller
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@ -81,6 +81,7 @@ system = System(cpu = cpus,
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funcmem = SimpleMemory(in_addr_map = False),
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funcmem = SimpleMemory(in_addr_map = False),
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physmem = SimpleMemory(null = True),
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physmem = SimpleMemory(null = True),
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funcbus = NoncoherentBus())
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funcbus = NoncoherentBus())
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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@ -40,6 +40,7 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory(),
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physmem = SimpleMemory(),
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membus = CoherentBus(width=16))
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membus = CoherentBus(width=16))
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system.clock = '1GHz'
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# l2cache & bus
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock="2GHz", width=16)
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system.toL2Bus = CoherentBus(clock="2GHz", width=16)
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@ -55,6 +55,7 @@ system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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cpu.connectAllPorts(system.membus)
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cpu.connectAllPorts(system.membus)
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@ -40,6 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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for cpu in cpus:
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for cpu in cpus:
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# create the interrupt controller
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# create the interrupt controller
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@ -39,6 +39,7 @@ system = System(cpu = cpus,
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physmem = DDR3_1600_x64(),
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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# l2cache & bus
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.toL2Bus = CoherentBus(clock = '2GHz')
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@ -42,6 +42,7 @@ system = System(cpu = cpu,
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physmem = ruby_memory,
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physmem = ruby_memory,
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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# create the interrupt controller
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# create the interrupt controller
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cpu.createInterruptController()
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cpu.createInterruptController()
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@ -44,6 +44,7 @@ system = System(cpu = cpu,
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physmem = DDR3_1600_x64(),
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physmem = DDR3_1600_x64(),
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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# create the interrupt controller
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# create the interrupt controller
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@ -78,6 +78,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
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wakeup_frequency = 10, num_cpus = options.num_cpus)
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wakeup_frequency = 10, num_cpus = options.num_cpus)
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system = System(tester = tester, physmem = SimpleMemory(null = True))
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system = System(tester = tester, physmem = SimpleMemory(null = True))
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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physmem = SimpleMemory(),
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physmem = SimpleMemory(),
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membus = CoherentBus())
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membus = CoherentBus())
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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system.cpu.addCheckerCpu()
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system.cpu.addCheckerCpu()
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@ -39,6 +39,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
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system.clock = '1GHz'
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# add L1 caches
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# add L1 caches
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for cpu in cpus:
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for cpu in cpus:
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@ -38,7 +38,7 @@ cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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system = System(cpu = cpus,
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system = System(cpu = cpus,
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physmem = SimpleMemory(range = AddrRange('1024MB')),
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physmem = SimpleMemory(range = AddrRange('1024MB')),
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membus = CoherentBus())
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membus = CoherentBus())
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system.clock = '1GHz'
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# l2cache & bus
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
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system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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system = System(cpu = AtomicSimpleCPU(cpu_id=0),
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physmem = SimpleMemory(),
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physmem = SimpleMemory(),
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membus = CoherentBus())
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membus = CoherentBus())
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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# create the interrupt controller
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# create the interrupt controller
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = SimpleMemory())
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system = System(cpu = cpus, physmem = SimpleMemory())
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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@ -36,6 +36,7 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
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system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
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system.clock = '1GHz'
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# l2cache & bus
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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system.toL2Bus = CoherentBus(clock = '2GHz')
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cpu = TimingSimpleCPU(cpu_id=0)
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cpu = TimingSimpleCPU(cpu_id=0)
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system = System(cpu = cpu, physmem = SimpleMemory(null = True))
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system = System(cpu = cpu, physmem = SimpleMemory(null = True))
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system.clock = options.sys_clock
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Ruby.create_system(options, system)
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Ruby.create_system(options, system)
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physmem = SimpleMemory(),
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physmem = SimpleMemory(),
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membus = CoherentBus(),
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membus = CoherentBus(),
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mem_mode = "timing")
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mem_mode = "timing")
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system.clock = '1GHz'
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system.system_port = system.membus.slave
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.physmem.port = system.membus.master
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# create the interrupt controller
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# create the interrupt controller
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@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
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# system simulated
|
# system simulated
|
||||||
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
|
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
|
||||||
membus = NoncoherentBus(width = 16))
|
membus = NoncoherentBus(width = 16))
|
||||||
|
system.clock = '1GHz'
|
||||||
|
|
||||||
# add a communication monitor
|
# add a communication monitor
|
||||||
system.monitor = CommMonitor()
|
system.monitor = CommMonitor()
|
||||||
|
|
|
@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
|
||||||
# system simulated
|
# system simulated
|
||||||
system = System(cpu = cpu, physmem = SimpleMemory(),
|
system = System(cpu = cpu, physmem = SimpleMemory(),
|
||||||
membus = NoncoherentBus(width = 16))
|
membus = NoncoherentBus(width = 16))
|
||||||
|
system.clock = '1GHz'
|
||||||
|
|
||||||
# add a communication monitor, and also trace all the packets
|
# add a communication monitor, and also trace all the packets
|
||||||
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
|
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
|
||||||
|
|
|
@ -34,6 +34,7 @@ from Benchmarks import *
|
||||||
|
|
||||||
test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
|
test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
|
||||||
SysConfig('netperf-stream-client.rcS'))
|
SysConfig('netperf-stream-client.rcS'))
|
||||||
|
test_sys.clock = '1GHz'
|
||||||
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
|
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
|
||||||
# create the interrupt controller
|
# create the interrupt controller
|
||||||
test_sys.cpu.createInterruptController()
|
test_sys.cpu.createInterruptController()
|
||||||
|
@ -48,6 +49,7 @@ test_sys.iobridge.master = test_sys.membus.slave
|
||||||
|
|
||||||
drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
|
drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
|
||||||
SysConfig('netperf-server.rcS'))
|
SysConfig('netperf-server.rcS'))
|
||||||
|
drive_sys.clock = '1GHz'
|
||||||
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
|
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
|
||||||
# create the interrupt controller
|
# create the interrupt controller
|
||||||
drive_sys.cpu.createInterruptController()
|
drive_sys.cpu.createInterruptController()
|
||||||
|
|
Loading…
Reference in a new issue