Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
This commit is contained in:
commit
075f4b108a
79 changed files with 1639 additions and 521 deletions
|
@ -38,14 +38,6 @@ class CowIdeDisk(IdeDisk):
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||||||
def childImage(self, ci):
|
def childImage(self, ci):
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self.image.child.image_file = ci
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self.image.child.image_file = ci
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|
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||||||
class CowMmDisk(MmDisk):
|
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||||||
image = CowDiskImage(child=RawDiskImage(read_only=True),
|
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||||||
read_only=False)
|
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||||||
|
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||||||
def childImage(self, ci):
|
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||||||
self.image.child.image_file = ci
|
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||||||
|
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||||||
|
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||||||
class BaseTsunami(Tsunami):
|
class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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pci_bus=0, pci_dev=1, pci_func=0)
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||||||
|
@ -87,6 +79,13 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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return self
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return self
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|
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def makeSparcSystem(mem_mode, mdesc = None):
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def makeSparcSystem(mem_mode, mdesc = None):
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class CowMmDisk(MmDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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|
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||||||
self = SparcSystem()
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self = SparcSystem()
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if not mdesc:
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if not mdesc:
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# generic system
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# generic system
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||||||
|
|
52
src/arch/alpha/AlphaSystem.py
Normal file
52
src/arch/alpha/AlphaSystem.py
Normal file
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@ -0,0 +1,52 @@
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||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
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||||||
|
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||||||
|
from m5.params import *
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|
from System import System
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|
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|
class AlphaSystem(System):
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|
type = 'AlphaSystem'
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|
console = Param.String("file that contains the console code")
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|
pal = Param.String("file that contains palcode")
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|
system_type = Param.UInt64("Type of system we are emulating")
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|
system_rev = Param.UInt64("Revision of system we are emulating")
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|
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class LinuxAlphaSystem(AlphaSystem):
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type = 'LinuxAlphaSystem'
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|
system_type = 34
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|
system_rev = 1 << 10
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||||||
|
|
||||||
|
class FreebsdAlphaSystem(AlphaSystem):
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|
type = 'FreebsdAlphaSystem'
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||||||
|
system_type = 34
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|
system_rev = 1 << 10
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||||||
|
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||||||
|
class Tru64AlphaSystem(AlphaSystem):
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|
type = 'Tru64AlphaSystem'
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||||||
|
system_type = 12
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||||||
|
system_rev = 2<<1
|
42
src/arch/alpha/AlphaTLB.py
Normal file
42
src/arch/alpha/AlphaTLB.py
Normal file
|
@ -0,0 +1,42 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
class AlphaTLB(SimObject):
|
||||||
|
type = 'AlphaTLB'
|
||||||
|
abstract = True
|
||||||
|
size = Param.Int("TLB size")
|
||||||
|
|
||||||
|
class AlphaDTB(AlphaTLB):
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||||||
|
type = 'AlphaDTB'
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||||||
|
size = 64
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||||||
|
|
||||||
|
class AlphaITB(AlphaTLB):
|
||||||
|
type = 'AlphaITB'
|
||||||
|
size = 48
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|
@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha':
|
||||||
Source('remote_gdb.cc')
|
Source('remote_gdb.cc')
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
|
SimObject('AlphaSystem.py')
|
||||||
|
SimObject('AlphaTLB.py')
|
||||||
|
|
||||||
Source('arguments.cc')
|
Source('arguments.cc')
|
||||||
Source('ev5.cc')
|
Source('ev5.cc')
|
||||||
Source('idle_event.cc')
|
Source('idle_event.cc')
|
||||||
|
|
|
@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc':
|
||||||
Source('remote_gdb.cc')
|
Source('remote_gdb.cc')
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
|
SimObject('SparcSystem.py')
|
||||||
|
SimObject('SparcTLB.py')
|
||||||
|
|
||||||
Source('arguments.cc')
|
Source('arguments.cc')
|
||||||
Source('pagetable.cc')
|
Source('pagetable.cc')
|
||||||
Source('stacktrace.cc')
|
Source('stacktrace.cc')
|
||||||
|
|
74
src/arch/sparc/SparcSystem.py
Normal file
74
src/arch/sparc/SparcSystem.py
Normal file
|
@ -0,0 +1,74 @@
|
||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
|
||||||
|
from PhysicalMemory import *
|
||||||
|
from System import System
|
||||||
|
|
||||||
|
class SparcSystem(System):
|
||||||
|
type = 'SparcSystem'
|
||||||
|
_rom_base = 0xfff0000000
|
||||||
|
_nvram_base = 0x1f11000000
|
||||||
|
_hypervisor_desc_base = 0x1f12080000
|
||||||
|
_partition_desc_base = 0x1f12000000
|
||||||
|
# ROM for OBP/Reset/Hypervisor
|
||||||
|
rom = Param.PhysicalMemory(
|
||||||
|
PhysicalMemory(range=AddrRange(_rom_base, size='8MB')),
|
||||||
|
"Memory to hold the ROM data")
|
||||||
|
# nvram
|
||||||
|
nvram = Param.PhysicalMemory(
|
||||||
|
PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')),
|
||||||
|
"Memory to hold the nvram data")
|
||||||
|
# hypervisor description
|
||||||
|
hypervisor_desc = Param.PhysicalMemory(
|
||||||
|
PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')),
|
||||||
|
"Memory to hold the hypervisor description")
|
||||||
|
# partition description
|
||||||
|
partition_desc = Param.PhysicalMemory(
|
||||||
|
PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')),
|
||||||
|
"Memory to hold the partition description")
|
||||||
|
|
||||||
|
reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
|
||||||
|
hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
|
||||||
|
"Address to load hypervisor at")
|
||||||
|
openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
|
||||||
|
"Address to load openboot at")
|
||||||
|
nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
|
||||||
|
hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
|
||||||
|
"Address for the hypervisor description")
|
||||||
|
partition_desc_addr = Param.Addr(_partition_desc_base,
|
||||||
|
"Address for the partition description")
|
||||||
|
|
||||||
|
reset_bin = Param.String("file that contains the reset code")
|
||||||
|
hypervisor_bin = Param.String("file that contains the hypervisor code")
|
||||||
|
openboot_bin = Param.String("file that contains the openboot code")
|
||||||
|
nvram_bin = Param.String("file that contains the contents of nvram")
|
||||||
|
hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
|
||||||
|
partition_desc_bin = Param.String("file that contains the partition description")
|
||||||
|
|
42
src/arch/sparc/SparcTLB.py
Normal file
42
src/arch/sparc/SparcTLB.py
Normal file
|
@ -0,0 +1,42 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Ali Saidi
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
class SparcTLB(SimObject):
|
||||||
|
type = 'SparcTLB'
|
||||||
|
abstract = True
|
||||||
|
size = Param.Int("TLB size")
|
||||||
|
|
||||||
|
class SparcDTB(SparcTLB):
|
||||||
|
type = 'SparcDTB'
|
||||||
|
size = 64
|
||||||
|
|
||||||
|
class SparcITB(SparcTLB):
|
||||||
|
type = 'SparcITB'
|
||||||
|
size = 64
|
|
@ -1,12 +1,45 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.SimObject import SimObject
|
from m5.SimObject import SimObject
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from m5 import build_env
|
from m5 import build_env
|
||||||
from AlphaTLB import AlphaDTB, AlphaITB
|
|
||||||
from SparcTLB import SparcDTB, SparcITB
|
|
||||||
from Bus import Bus
|
from Bus import Bus
|
||||||
import sys
|
import sys
|
||||||
|
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
if build_env['TARGET_ISA'] == 'alpha':
|
||||||
|
from AlphaTLB import AlphaDTB, AlphaITB
|
||||||
|
|
||||||
|
if build_env['TARGET_ISA'] == 'sparc':
|
||||||
|
from SparcTLB import SparcDTB, SparcITB
|
||||||
|
|
||||||
class BaseCPU(SimObject):
|
class BaseCPU(SimObject):
|
||||||
type = 'BaseCPU'
|
type = 'BaseCPU'
|
||||||
abstract = True
|
abstract = True
|
46
src/cpu/FuncUnit.py
Normal file
46
src/cpu/FuncUnit.py
Normal file
|
@ -0,0 +1,46 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
|
||||||
|
class OpType(Enum):
|
||||||
|
vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
|
||||||
|
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
|
||||||
|
'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
|
||||||
|
|
||||||
|
class OpDesc(SimObject):
|
||||||
|
type = 'OpDesc'
|
||||||
|
issueLat = Param.Int(1, "cycles until another can be issued")
|
||||||
|
opClass = Param.OpType("type of operation")
|
||||||
|
opLat = Param.Int(1, "cycles until result is available")
|
||||||
|
|
||||||
|
class FUDesc(SimObject):
|
||||||
|
type = 'FUDesc'
|
||||||
|
count = Param.Int("number of these FU's available")
|
||||||
|
opList = VectorParam.OpDesc("operation classes for this FU type")
|
34
src/cpu/IntrControl.py
Normal file
34
src/cpu/IntrControl.py
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
class IntrControl(SimObject):
|
||||||
|
type = 'IntrControl'
|
||||||
|
sys = Param.System(Parent.any, "the system we are part of")
|
|
@ -103,6 +103,9 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
|
||||||
# and one of these are not being used.
|
# and one of these are not being used.
|
||||||
CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
|
CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
|
||||||
|
|
||||||
|
SimObject('BaseCPU.py')
|
||||||
|
SimObject('FuncUnit.py')
|
||||||
|
|
||||||
Source('activity.cc')
|
Source('activity.cc')
|
||||||
Source('base.cc')
|
Source('base.cc')
|
||||||
Source('cpuevent.cc')
|
Source('cpuevent.cc')
|
||||||
|
@ -116,6 +119,8 @@ Source('simple_thread.cc')
|
||||||
Source('thread_state.cc')
|
Source('thread_state.cc')
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
|
SimObject('IntrControl.py')
|
||||||
|
|
||||||
Source('intr_control.cc')
|
Source('intr_control.cc')
|
||||||
Source('profile.cc')
|
Source('profile.cc')
|
||||||
|
|
||||||
|
|
52
src/cpu/memtest/MemTest.py
Normal file
52
src/cpu/memtest/MemTest.py
Normal file
|
@ -0,0 +1,52 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from m5 import build_env
|
||||||
|
|
||||||
|
class MemTest(SimObject):
|
||||||
|
type = 'MemTest'
|
||||||
|
max_loads = Param.Counter("number of loads to execute")
|
||||||
|
atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
|
||||||
|
memory_size = Param.Int(65536, "memory size")
|
||||||
|
percent_dest_unaligned = Param.Percent(50,
|
||||||
|
"percent of copy dest address that are unaligned")
|
||||||
|
percent_reads = Param.Percent(65, "target read percentage")
|
||||||
|
percent_source_unaligned = Param.Percent(50,
|
||||||
|
"percent of copy source address that are unaligned")
|
||||||
|
percent_functional = Param.Percent(50, "percent of access that are functional")
|
||||||
|
percent_uncacheable = Param.Percent(10,
|
||||||
|
"target uncacheable percentage")
|
||||||
|
progress_interval = Param.Counter(1000000,
|
||||||
|
"progress report interval (in accesses)")
|
||||||
|
trace_addr = Param.Addr(0, "address to trace")
|
||||||
|
|
||||||
|
test = Port("Port to the memory system to test")
|
||||||
|
functional = Port("Port to the functional memory used for verification")
|
|
@ -31,4 +31,6 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if 'O3CPU' in env['CPU_MODELS']:
|
if 'O3CPU' in env['CPU_MODELS']:
|
||||||
|
SimObject('MemTest.py')
|
||||||
|
|
||||||
Source('memtest.cc')
|
Source('memtest.cc')
|
||||||
|
|
40
src/cpu/o3/FUPool.py
Normal file
40
src/cpu/o3/FUPool.py
Normal file
|
@ -0,0 +1,40 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from FuncUnit import *
|
||||||
|
from FuncUnitConfig import *
|
||||||
|
|
||||||
|
class FUPool(SimObject):
|
||||||
|
type = 'FUPool'
|
||||||
|
FUList = VectorParam.FUDesc("list of FU's for this pool")
|
||||||
|
|
||||||
|
class DefaultFUPool(FUPool):
|
||||||
|
FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
|
||||||
|
WritePort(), RdWrPort(), IprPort() ]
|
69
src/cpu/o3/FuncUnitConfig.py
Normal file
69
src/cpu/o3/FuncUnitConfig.py
Normal file
|
@ -0,0 +1,69 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from FuncUnit import *
|
||||||
|
|
||||||
|
class IntALU(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='IntAlu') ]
|
||||||
|
count = 6
|
||||||
|
|
||||||
|
class IntMultDiv(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='IntMult', opLat=3),
|
||||||
|
OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
|
||||||
|
count=2
|
||||||
|
|
||||||
|
class FP_ALU(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='FloatAdd', opLat=2),
|
||||||
|
OpDesc(opClass='FloatCmp', opLat=2),
|
||||||
|
OpDesc(opClass='FloatCvt', opLat=2) ]
|
||||||
|
count = 4
|
||||||
|
|
||||||
|
class FP_MultDiv(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='FloatMult', opLat=4),
|
||||||
|
OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
|
||||||
|
OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
|
||||||
|
count = 2
|
||||||
|
|
||||||
|
class ReadPort(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='MemRead') ]
|
||||||
|
count = 0
|
||||||
|
|
||||||
|
class WritePort(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='MemWrite') ]
|
||||||
|
count = 0
|
||||||
|
|
||||||
|
class RdWrPort(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
|
||||||
|
count = 4
|
||||||
|
|
||||||
|
class IprPort(FUDesc):
|
||||||
|
opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
|
||||||
|
count = 1
|
||||||
|
|
|
@ -1,10 +1,40 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from m5 import build_env
|
from m5 import build_env
|
||||||
from BaseCPU import BaseCPU
|
from BaseCPU import BaseCPU
|
||||||
from Checker import O3Checker
|
|
||||||
from FUPool import *
|
from FUPool import *
|
||||||
|
|
||||||
|
if build_env['USE_CHECKER']:
|
||||||
|
from O3Checker import O3Checker
|
||||||
|
|
||||||
class DerivO3CPU(BaseCPU):
|
class DerivO3CPU(BaseCPU):
|
||||||
type = 'DerivO3CPU'
|
type = 'DerivO3CPU'
|
||||||
activity = Param.Unsigned(0, "Initial count")
|
activity = Param.Unsigned(0, "Initial count")
|
43
src/cpu/o3/O3Checker.py
Normal file
43
src/cpu/o3/O3Checker.py
Normal file
|
@ -0,0 +1,43 @@
|
||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5 import build_env
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class O3Checker(BaseCPU):
|
||||||
|
type = 'O3Checker'
|
||||||
|
exitOnError = Param.Bool(False, "Exit on an error")
|
||||||
|
updateOnError = Param.Bool(False,
|
||||||
|
"Update the checker with the main CPU's state on an error")
|
||||||
|
warnOnlyOnLoadError = Param.Bool(False,
|
||||||
|
"If a load result is incorrect, only print a warning and do not exit")
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
profile = Param.Latency('0ns', "trace the kernel stack")
|
|
@ -33,6 +33,10 @@ import sys
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if 'O3CPU' in env['CPU_MODELS']:
|
if 'O3CPU' in env['CPU_MODELS']:
|
||||||
|
SimObject('FUPool.py')
|
||||||
|
SimObject('FuncUnitConfig.py')
|
||||||
|
SimObject('O3CPU.py')
|
||||||
|
|
||||||
Source('base_dyn_inst.cc')
|
Source('base_dyn_inst.cc')
|
||||||
Source('bpred_unit.cc')
|
Source('bpred_unit.cc')
|
||||||
Source('commit.cc')
|
Source('commit.cc')
|
||||||
|
@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']:
|
||||||
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
|
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
|
||||||
|
|
||||||
if env['USE_CHECKER']:
|
if env['USE_CHECKER']:
|
||||||
|
SimObject('m5/objects/O3Checker.py')
|
||||||
Source('checker_builder.cc')
|
Source('checker_builder.cc')
|
||||||
|
|
||||||
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
|
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
|
||||||
|
|
|
@ -1,12 +1,44 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5 import build_env
|
from m5 import build_env
|
||||||
from BaseCPU import BaseCPU
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
if build_env['USE_CHECKER']:
|
||||||
|
from OzoneChecker import OzoneChecker
|
||||||
|
|
||||||
class DerivOzoneCPU(BaseCPU):
|
class DerivOzoneCPU(BaseCPU):
|
||||||
type = 'DerivOzoneCPU'
|
type = 'DerivOzoneCPU'
|
||||||
|
|
||||||
numThreads = Param.Unsigned("number of HW thread contexts")
|
numThreads = Param.Unsigned("number of HW thread contexts")
|
||||||
|
|
||||||
|
if build_env['USE_CHECKER']:
|
||||||
checker = Param.BaseCPU("Checker CPU")
|
checker = Param.BaseCPU("Checker CPU")
|
||||||
if build_env['FULL_SYSTEM']:
|
if build_env['FULL_SYSTEM']:
|
||||||
profile = Param.Latency('0ns', "trace the kernel stack")
|
profile = Param.Latency('0ns', "trace the kernel stack")
|
43
src/cpu/ozone/OzoneChecker.py
Normal file
43
src/cpu/ozone/OzoneChecker.py
Normal file
|
@ -0,0 +1,43 @@
|
||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5 import build_env
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class OzoneChecker(BaseCPU):
|
||||||
|
type = 'OzoneChecker'
|
||||||
|
exitOnError = Param.Bool(False, "Exit on an error")
|
||||||
|
updateOnError = Param.Bool(False,
|
||||||
|
"Update the checker with the main CPU's state on an error")
|
||||||
|
warnOnlyOnLoadError = Param.Bool(False,
|
||||||
|
"If a load result is incorrect, only print a warning and do not exit")
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
profile = Param.Latency('0ns', "trace the kernel stack")
|
|
@ -31,6 +31,9 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if 'OzoneCPU' in env['CPU_MODELS']:
|
if 'OzoneCPU' in env['CPU_MODELS']:
|
||||||
|
SimObject('OzoneCPU.py')
|
||||||
|
SimObject('SimpleOzoneCPU.py')
|
||||||
|
|
||||||
need_bp_unit = True
|
need_bp_unit = True
|
||||||
Source('base_dyn_inst.cc')
|
Source('base_dyn_inst.cc')
|
||||||
Source('bpred_unit.cc')
|
Source('bpred_unit.cc')
|
||||||
|
@ -42,4 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']:
|
||||||
Source('lw_lsq.cc')
|
Source('lw_lsq.cc')
|
||||||
Source('rename_table.cc')
|
Source('rename_table.cc')
|
||||||
if env['USE_CHECKER']:
|
if env['USE_CHECKER']:
|
||||||
|
SimObject('m5/objects/OzoneChecker.py')
|
||||||
Source('checker_builder.cc')
|
Source('checker_builder.cc')
|
||||||
|
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Kevin Lim
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5 import build_env
|
from m5 import build_env
|
||||||
from BaseCPU import BaseCPU
|
from BaseCPU import BaseCPU
|
43
src/cpu/simple/AtomicSimpleCPU.py
Normal file
43
src/cpu/simple/AtomicSimpleCPU.py
Normal file
|
@ -0,0 +1,43 @@
|
||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5 import build_env
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class AtomicSimpleCPU(BaseCPU):
|
||||||
|
type = 'AtomicSimpleCPU'
|
||||||
|
width = Param.Int(1, "CPU width")
|
||||||
|
simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
profile = Param.Latency('0ns', "trace the kernel stack")
|
||||||
|
icache_port = Port("Instruction Port")
|
||||||
|
dcache_port = Port("Data Port")
|
||||||
|
_mem_ports = ['icache_port', 'dcache_port']
|
|
@ -33,10 +33,12 @@ Import('*')
|
||||||
need_simple_base = False
|
need_simple_base = False
|
||||||
if 'AtomicSimpleCPU' in env['CPU_MODELS']:
|
if 'AtomicSimpleCPU' in env['CPU_MODELS']:
|
||||||
need_simple_base = True
|
need_simple_base = True
|
||||||
|
SimObject('AtomicSimpleCPU.py')
|
||||||
Source('atomic.cc')
|
Source('atomic.cc')
|
||||||
|
|
||||||
if 'TimingSimpleCPU' in env['CPU_MODELS']:
|
if 'TimingSimpleCPU' in env['CPU_MODELS']:
|
||||||
need_simple_base = True
|
need_simple_base = True
|
||||||
|
SimObject('TimingSimpleCPU.py')
|
||||||
Source('timing.cc')
|
Source('timing.cc')
|
||||||
|
|
||||||
if need_simple_base:
|
if need_simple_base:
|
||||||
|
|
41
src/cpu/simple/TimingSimpleCPU.py
Normal file
41
src/cpu/simple/TimingSimpleCPU.py
Normal file
|
@ -0,0 +1,41 @@
|
||||||
|
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5 import build_env
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class TimingSimpleCPU(BaseCPU):
|
||||||
|
type = 'TimingSimpleCPU'
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
profile = Param.Latency('0ns', "trace the kernel stack")
|
||||||
|
icache_port = Port("Instruction Port")
|
||||||
|
dcache_port = Port("Data Port")
|
||||||
|
_mem_ports = ['icache_port', 'dcache_port']
|
34
src/dev/BadDevice.py
Normal file
34
src/dev/BadDevice.py
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from Device import BasicPioDevice
|
||||||
|
|
||||||
|
class BadDevice(BasicPioDevice):
|
||||||
|
type = 'BadDevice'
|
||||||
|
devicename = Param.String("Name of device to error on")
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from MemObject import MemObject
|
from MemObject import MemObject
|
44
src/dev/DiskImage.py
Normal file
44
src/dev/DiskImage.py
Normal file
|
@ -0,0 +1,44 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
class DiskImage(SimObject):
|
||||||
|
type = 'DiskImage'
|
||||||
|
abstract = True
|
||||||
|
image_file = Param.String("disk image file")
|
||||||
|
read_only = Param.Bool(False, "read only image")
|
||||||
|
|
||||||
|
class RawDiskImage(DiskImage):
|
||||||
|
type = 'RawDiskImage'
|
||||||
|
|
||||||
|
class CowDiskImage(DiskImage):
|
||||||
|
type = 'CowDiskImage'
|
||||||
|
child = Param.DiskImage(RawDiskImage(read_only=True),
|
||||||
|
"child image")
|
||||||
|
table_size = Param.Int(65536, "initial table size")
|
|
@ -1,8 +1,34 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.SimObject import SimObject
|
from m5.SimObject import SimObject
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from m5 import build_env
|
|
||||||
from Device import DmaDevice
|
|
||||||
from Pci import PciDevice, PciConfigData
|
from Pci import PciDevice, PciConfigData
|
||||||
|
|
||||||
class EtherInt(SimObject):
|
class EtherInt(SimObject):
|
||||||
|
@ -36,46 +62,19 @@ class EtherDump(SimObject):
|
||||||
file = Param.String("dump file")
|
file = Param.String("dump file")
|
||||||
maxlen = Param.Int(96, "max portion of packet data to dump")
|
maxlen = Param.Int(96, "max portion of packet data to dump")
|
||||||
|
|
||||||
if build_env['ALPHA_TLASER']:
|
|
||||||
|
|
||||||
class EtherDev(DmaDevice):
|
|
||||||
type = 'EtherDev'
|
|
||||||
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
|
||||||
"Ethernet Hardware Address")
|
|
||||||
|
|
||||||
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
|
||||||
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
|
||||||
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
|
||||||
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
|
||||||
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
|
|
||||||
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
|
|
||||||
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
|
|
||||||
|
|
||||||
rx_filter = Param.Bool(True, "Enable Receive Filter")
|
|
||||||
rx_delay = Param.Latency('1us', "Receive Delay")
|
|
||||||
tx_delay = Param.Latency('1us', "Transmit Delay")
|
|
||||||
|
|
||||||
intr_delay = Param.Latency('0us', "Interrupt Delay")
|
|
||||||
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
|
||||||
physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
|
|
||||||
tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
|
|
||||||
|
|
||||||
class EtherDevInt(EtherInt):
|
|
||||||
type = 'EtherDevInt'
|
|
||||||
device = Param.EtherDev("Ethernet device of this interface")
|
|
||||||
|
|
||||||
|
|
||||||
class IGbE(PciDevice):
|
class IGbE(PciDevice):
|
||||||
type = 'IGbE'
|
type = 'IGbE'
|
||||||
hardware_address = Param.String("Ethernet Hardware Address")
|
hardware_address = Param.String("Ethernet Hardware Address")
|
||||||
use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)")
|
use_flow_control = Param.Bool(False,
|
||||||
|
"Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
|
||||||
rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
|
rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
|
||||||
tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
|
tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
|
||||||
rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
|
rx_desc_cache_size = Param.Int(64,
|
||||||
tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
|
"Number of enteries in the rx descriptor cache")
|
||||||
|
tx_desc_cache_size = Param.Int(64,
|
||||||
|
"Number of enteries in the rx descriptor cache")
|
||||||
clock = Param.Clock('500MHz', "Clock speed of the device")
|
clock = Param.Clock('500MHz', "Clock speed of the device")
|
||||||
|
|
||||||
|
|
||||||
class IGbEPciData(PciConfigData):
|
class IGbEPciData(PciConfigData):
|
||||||
VendorID = 0x8086
|
VendorID = 0x8086
|
||||||
DeviceID = 0x1075
|
DeviceID = 0x1075
|
68
src/dev/Ide.py
Normal file
68
src/dev/Ide.py
Normal file
|
@ -0,0 +1,68 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from Pci import PciDevice, PciConfigData
|
||||||
|
|
||||||
|
class IdeID(Enum): vals = ['master', 'slave']
|
||||||
|
|
||||||
|
class IdeControllerPciData(PciConfigData):
|
||||||
|
VendorID = 0x8086
|
||||||
|
DeviceID = 0x7111
|
||||||
|
Command = 0x0
|
||||||
|
Status = 0x280
|
||||||
|
Revision = 0x0
|
||||||
|
ClassCode = 0x01
|
||||||
|
SubClassCode = 0x01
|
||||||
|
ProgIF = 0x85
|
||||||
|
BAR0 = 0x00000001
|
||||||
|
BAR1 = 0x00000001
|
||||||
|
BAR2 = 0x00000001
|
||||||
|
BAR3 = 0x00000001
|
||||||
|
BAR4 = 0x00000001
|
||||||
|
BAR5 = 0x00000001
|
||||||
|
InterruptLine = 0x1f
|
||||||
|
InterruptPin = 0x01
|
||||||
|
BAR0Size = '8B'
|
||||||
|
BAR1Size = '4B'
|
||||||
|
BAR2Size = '8B'
|
||||||
|
BAR3Size = '4B'
|
||||||
|
BAR4Size = '16B'
|
||||||
|
|
||||||
|
class IdeDisk(SimObject):
|
||||||
|
type = 'IdeDisk'
|
||||||
|
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
|
||||||
|
driveID = Param.IdeID('master', "Drive ID")
|
||||||
|
image = Param.DiskImage("Disk image")
|
||||||
|
|
||||||
|
class IdeController(PciDevice):
|
||||||
|
type = 'IdeController'
|
||||||
|
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
|
||||||
|
|
||||||
|
configdata =IdeControllerPciData()
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.SimObject import SimObject
|
from m5.SimObject import SimObject
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
35
src/dev/Platform.py
Normal file
35
src/dev/Platform.py
Normal file
|
@ -0,0 +1,35 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
class Platform(SimObject):
|
||||||
|
type = 'Platform'
|
||||||
|
abstract = True
|
||||||
|
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
|
|
@ -32,6 +32,17 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
|
SimObject('BadDevice.py')
|
||||||
|
SimObject('Device.py')
|
||||||
|
SimObject('DiskImage.py')
|
||||||
|
SimObject('Ethernet.py')
|
||||||
|
SimObject('Ide.py')
|
||||||
|
SimObject('Pci.py')
|
||||||
|
SimObject('Platform.py')
|
||||||
|
SimObject('SimConsole.py')
|
||||||
|
SimObject('SimpleDisk.py')
|
||||||
|
SimObject('Uart.py')
|
||||||
|
|
||||||
Source('baddev.cc')
|
Source('baddev.cc')
|
||||||
Source('disk_image.cc')
|
Source('disk_image.cc')
|
||||||
Source('etherbus.cc')
|
Source('etherbus.cc')
|
||||||
|
|
39
src/dev/SimConsole.py
Normal file
39
src/dev/SimConsole.py
Normal file
|
@ -0,0 +1,39 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
|
||||||
|
class SimConsole(SimObject):
|
||||||
|
type = 'SimConsole'
|
||||||
|
append_name = Param.Bool(True, "append name() to filename")
|
||||||
|
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
|
||||||
|
port = Param.TcpPort(3456, "listen port")
|
||||||
|
number = Param.Int(0, "console number")
|
||||||
|
output = Param.String('console', "file to dump output to")
|
35
src/dev/SimpleDisk.py
Normal file
35
src/dev/SimpleDisk.py
Normal file
|
@ -0,0 +1,35 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
class SimpleDisk(SimObject):
|
||||||
|
type = 'SimpleDisk'
|
||||||
|
disk = Param.DiskImage("Disk Image")
|
||||||
|
system = Param.System(Parent.any, "Sysetm Pointer")
|
45
src/dev/Uart.py
Normal file
45
src/dev/Uart.py
Normal file
|
@ -0,0 +1,45 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from m5 import build_env
|
||||||
|
from Device import BasicPioDevice
|
||||||
|
|
||||||
|
class Uart(BasicPioDevice):
|
||||||
|
type = 'Uart'
|
||||||
|
abstract = True
|
||||||
|
sim_console = Param.SimConsole(Parent.any, "The console")
|
||||||
|
|
||||||
|
class Uart8250(Uart):
|
||||||
|
type = 'Uart8250'
|
||||||
|
|
||||||
|
if build_env['ALPHA_TLASER']:
|
||||||
|
class Uart8530(Uart):
|
||||||
|
type = 'Uart8530'
|
||||||
|
|
38
src/dev/alpha/AlphaConsole.py
Normal file
38
src/dev/alpha/AlphaConsole.py
Normal file
|
@ -0,0 +1,38 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from Device import BasicPioDevice
|
||||||
|
|
||||||
|
class AlphaConsole(BasicPioDevice):
|
||||||
|
type = 'AlphaConsole'
|
||||||
|
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
|
||||||
|
disk = Param.SimpleDisk("Simple Disk")
|
||||||
|
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
|
||||||
|
system = Param.AlphaSystem(Parent.any, "system object")
|
|
@ -32,6 +32,9 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
|
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
|
||||||
|
SimObject('AlphaConsole.py')
|
||||||
|
SimObject('Tsunami.py')
|
||||||
|
|
||||||
Source('console.cc')
|
Source('console.cc')
|
||||||
Source('tsunami.cc')
|
Source('tsunami.cc')
|
||||||
Source('tsunami_cchip.cc')
|
Source('tsunami_cchip.cc')
|
||||||
|
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from Device import BasicPioDevice, IsaFake, BadAddr
|
from Device import BasicPioDevice, IsaFake, BadAddr
|
|
@ -32,6 +32,8 @@
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
|
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
|
||||||
|
SimObject('T1000.py')
|
||||||
|
|
||||||
Source('dtod.cc')
|
Source('dtod.cc')
|
||||||
Source('iob.cc')
|
Source('iob.cc')
|
||||||
Source('t1000.cc')
|
Source('t1000.cc')
|
||||||
|
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Gabe Black
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
|
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
|
44
src/mem/Bridge.py
Normal file
44
src/mem/Bridge.py
Normal file
|
@ -0,0 +1,44 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Ali Saidi
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from MemObject import MemObject
|
||||||
|
|
||||||
|
class Bridge(MemObject):
|
||||||
|
type = 'Bridge'
|
||||||
|
side_a = Port('Side A port')
|
||||||
|
side_b = Port('Side B port')
|
||||||
|
req_size_a = Param.Int(16, "The number of requests to buffer")
|
||||||
|
req_size_b = Param.Int(16, "The number of requests to buffer")
|
||||||
|
resp_size_a = Param.Int(16, "The number of requests to buffer")
|
||||||
|
resp_size_b = Param.Int(16, "The number of requests to buffer")
|
||||||
|
delay = Param.Latency('0ns', "The latency of this bridge")
|
||||||
|
nack_delay = Param.Latency('0ns', "The latency of this bridge")
|
||||||
|
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
||||||
|
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
|
||||||
|
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
|
49
src/mem/Bus.py
Normal file
49
src/mem/Bus.py
Normal file
|
@ -0,0 +1,49 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5 import build_env
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from MemObject import MemObject
|
||||||
|
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
from Device import BadAddr
|
||||||
|
|
||||||
|
class Bus(MemObject):
|
||||||
|
type = 'Bus'
|
||||||
|
port = VectorPort("vector port for connecting devices")
|
||||||
|
bus_id = Param.Int(0, "blah")
|
||||||
|
clock = Param.Clock("1GHz", "bus clock speed")
|
||||||
|
width = Param.Int(64, "bus width (bytes)")
|
||||||
|
responder_set = Param.Bool(False, "Did the user specify a default responder.")
|
||||||
|
block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
|
||||||
|
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
|
||||||
|
else:
|
||||||
|
default = Port("Default port for requests that aren't handled by a device.")
|
34
src/mem/MemObject.py
Normal file
34
src/mem/MemObject.py
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Ron Dreslinski
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
|
||||||
|
class MemObject(SimObject):
|
||||||
|
type = 'MemObject'
|
||||||
|
abstract = True
|
57
src/mem/PhysicalMemory.py
Normal file
57
src/mem/PhysicalMemory.py
Normal file
|
@ -0,0 +1,57 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from MemObject import *
|
||||||
|
|
||||||
|
class PhysicalMemory(MemObject):
|
||||||
|
type = 'PhysicalMemory'
|
||||||
|
port = VectorPort("the access port")
|
||||||
|
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
|
||||||
|
file = Param.String('', "memory mapped file")
|
||||||
|
latency = Param.Latency('1t', "latency of an access")
|
||||||
|
zero = Param.Bool(False, "zero initialize memory")
|
||||||
|
|
||||||
|
class DRAMMemory(PhysicalMemory):
|
||||||
|
type = 'DRAMMemory'
|
||||||
|
# Many of these should be observed from the configuration
|
||||||
|
cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
|
||||||
|
mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
|
||||||
|
mem_actpolicy = Param.String("open", "Open/Close policy")
|
||||||
|
memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
|
||||||
|
bus_width = Param.Int(16, "")
|
||||||
|
act_lat = Param.Int(2, "RAS to CAS delay")
|
||||||
|
cas_lat = Param.Int(1, "CAS delay")
|
||||||
|
war_lat = Param.Int(2, "write after read delay")
|
||||||
|
pre_lat = Param.Int(2, "precharge delay")
|
||||||
|
dpl_lat = Param.Int(2, "data in to precharge delay")
|
||||||
|
trc_lat = Param.Int(6, "row cycle delay")
|
||||||
|
num_banks = Param.Int(4, "Number of Banks")
|
||||||
|
num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
|
||||||
|
|
|
@ -30,6 +30,11 @@
|
||||||
|
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
|
SimObject('Bridge.py')
|
||||||
|
SimObject('Bus.py')
|
||||||
|
SimObject('PhysicalMemory.py')
|
||||||
|
SimObject('MemObject.py')
|
||||||
|
|
||||||
Source('bridge.cc')
|
Source('bridge.cc')
|
||||||
Source('bus.cc')
|
Source('bus.cc')
|
||||||
Source('dram.cc')
|
Source('dram.cc')
|
||||||
|
|
|
@ -1,3 +1,31 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from MemObject import MemObject
|
from MemObject import MemObject
|
||||||
|
|
2
src/mem/cache/SConscript
vendored
2
src/mem/cache/SConscript
vendored
|
@ -30,6 +30,8 @@
|
||||||
|
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
|
SimObject('BaseCache.py')
|
||||||
|
|
||||||
Source('base_cache.cc')
|
Source('base_cache.cc')
|
||||||
Source('cache.cc')
|
Source('cache.cc')
|
||||||
Source('cache_builder.cc')
|
Source('cache_builder.cc')
|
||||||
|
|
2
src/mem/cache/coherence/SConscript
vendored
2
src/mem/cache/coherence/SConscript
vendored
|
@ -30,5 +30,7 @@
|
||||||
|
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
|
SimObject('CoherenceProtocol.py')
|
||||||
|
|
||||||
Source('coherence_protocol.cc')
|
Source('coherence_protocol.cc')
|
||||||
|
|
||||||
|
|
1
src/mem/cache/tags/SConscript
vendored
1
src/mem/cache/tags/SConscript
vendored
|
@ -38,5 +38,6 @@ Source('split.cc')
|
||||||
Source('split_lifo.cc')
|
Source('split_lifo.cc')
|
||||||
Source('split_lru.cc')
|
Source('split_lru.cc')
|
||||||
|
|
||||||
|
SimObject('Repl.py')
|
||||||
Source('repl/gen.cc')
|
Source('repl/gen.cc')
|
||||||
Source('repl/repl.cc')
|
Source('repl/repl.cc')
|
||||||
|
|
|
@ -60,54 +60,3 @@ SwigSource('m5.internal', 'swig/sim_object.i')
|
||||||
SwigSource('m5.internal', 'swig/stats.i')
|
SwigSource('m5.internal', 'swig/stats.i')
|
||||||
SwigSource('m5.internal', 'swig/trace.i')
|
SwigSource('m5.internal', 'swig/trace.i')
|
||||||
PySource('m5.internal', 'm5/internal/__init__.py')
|
PySource('m5.internal', 'm5/internal/__init__.py')
|
||||||
|
|
||||||
SimObject('m5/objects/AlphaConsole.py')
|
|
||||||
SimObject('m5/objects/AlphaTLB.py')
|
|
||||||
SimObject('m5/objects/BadDevice.py')
|
|
||||||
SimObject('m5/objects/BaseCPU.py')
|
|
||||||
SimObject('m5/objects/BaseCache.py')
|
|
||||||
SimObject('m5/objects/BaseHier.py')
|
|
||||||
SimObject('m5/objects/BaseMem.py')
|
|
||||||
SimObject('m5/objects/BaseMemory.py')
|
|
||||||
SimObject('m5/objects/BranchPred.py')
|
|
||||||
SimObject('m5/objects/Bridge.py')
|
|
||||||
SimObject('m5/objects/Bus.py')
|
|
||||||
SimObject('m5/objects/Checker.py')
|
|
||||||
SimObject('m5/objects/CoherenceProtocol.py')
|
|
||||||
SimObject('m5/objects/DRAMMemory.py')
|
|
||||||
SimObject('m5/objects/Device.py')
|
|
||||||
SimObject('m5/objects/DiskImage.py')
|
|
||||||
SimObject('m5/objects/Ethernet.py')
|
|
||||||
SimObject('m5/objects/FUPool.py')
|
|
||||||
SimObject('m5/objects/FastCPU.py')
|
|
||||||
#SimObject('m5/objects/FreebsdSystem.py')
|
|
||||||
SimObject('m5/objects/FuncUnit.py')
|
|
||||||
SimObject('m5/objects/FuncUnitConfig.py')
|
|
||||||
SimObject('m5/objects/FunctionalMemory.py')
|
|
||||||
SimObject('m5/objects/HierParams.py')
|
|
||||||
SimObject('m5/objects/Ide.py')
|
|
||||||
SimObject('m5/objects/IntrControl.py')
|
|
||||||
SimObject('m5/objects/LinuxSystem.py')
|
|
||||||
SimObject('m5/objects/MainMemory.py')
|
|
||||||
SimObject('m5/objects/MemObject.py')
|
|
||||||
SimObject('m5/objects/MemTest.py')
|
|
||||||
SimObject('m5/objects/MemoryController.py')
|
|
||||||
SimObject('m5/objects/O3CPU.py')
|
|
||||||
SimObject('m5/objects/OzoneCPU.py')
|
|
||||||
SimObject('m5/objects/Pci.py')
|
|
||||||
SimObject('m5/objects/PhysicalMemory.py')
|
|
||||||
SimObject('m5/objects/Platform.py')
|
|
||||||
SimObject('m5/objects/Process.py')
|
|
||||||
SimObject('m5/objects/Repl.py')
|
|
||||||
SimObject('m5/objects/Root.py')
|
|
||||||
SimObject('m5/objects/Sampler.py')
|
|
||||||
SimObject('m5/objects/SimConsole.py')
|
|
||||||
SimObject('m5/objects/SimpleCPU.py')
|
|
||||||
SimObject('m5/objects/SimpleDisk.py')
|
|
||||||
#SimObject('m5/objects/SimpleOzoneCPU.py')
|
|
||||||
SimObject('m5/objects/SparcTLB.py')
|
|
||||||
SimObject('m5/objects/System.py')
|
|
||||||
SimObject('m5/objects/T1000.py')
|
|
||||||
#SimObject('m5/objects/Tru64System.py')
|
|
||||||
SimObject('m5/objects/Tsunami.py')
|
|
||||||
SimObject('m5/objects/Uart.py')
|
|
||||||
|
|
|
@ -1,10 +0,0 @@
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from Device import BasicPioDevice
|
|
||||||
|
|
||||||
class AlphaConsole(BasicPioDevice):
|
|
||||||
type = 'AlphaConsole'
|
|
||||||
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
|
|
||||||
disk = Param.SimpleDisk("Simple Disk")
|
|
||||||
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
|
|
||||||
system = Param.AlphaSystem(Parent.any, "system object")
|
|
|
@ -1,14 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
class AlphaTLB(SimObject):
|
|
||||||
type = 'AlphaTLB'
|
|
||||||
abstract = True
|
|
||||||
size = Param.Int("TLB size")
|
|
||||||
|
|
||||||
class AlphaDTB(AlphaTLB):
|
|
||||||
type = 'AlphaDTB'
|
|
||||||
size = 64
|
|
||||||
|
|
||||||
class AlphaITB(AlphaTLB):
|
|
||||||
type = 'AlphaITB'
|
|
||||||
size = 48
|
|
|
@ -1,6 +0,0 @@
|
||||||
from m5.params import *
|
|
||||||
from Device import BasicPioDevice
|
|
||||||
|
|
||||||
class BadDevice(BasicPioDevice):
|
|
||||||
type = 'BadDevice'
|
|
||||||
devicename = Param.String("Name of device to error on")
|
|
|
@ -1,16 +0,0 @@
|
||||||
from m5.params import *
|
|
||||||
from MemObject import MemObject
|
|
||||||
|
|
||||||
class Bridge(MemObject):
|
|
||||||
type = 'Bridge'
|
|
||||||
side_a = Port('Side A port')
|
|
||||||
side_b = Port('Side B port')
|
|
||||||
req_size_a = Param.Int(16, "The number of requests to buffer")
|
|
||||||
req_size_b = Param.Int(16, "The number of requests to buffer")
|
|
||||||
resp_size_a = Param.Int(16, "The number of requests to buffer")
|
|
||||||
resp_size_b = Param.Int(16, "The number of requests to buffer")
|
|
||||||
delay = Param.Latency('0ns', "The latency of this bridge")
|
|
||||||
nack_delay = Param.Latency('0ns', "The latency of this bridge")
|
|
||||||
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
|
||||||
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
|
|
||||||
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
|
|
|
@ -1,19 +0,0 @@
|
||||||
from m5 import build_env
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from MemObject import MemObject
|
|
||||||
from Device import BadAddr
|
|
||||||
|
|
||||||
class Bus(MemObject):
|
|
||||||
type = 'Bus'
|
|
||||||
port = VectorPort("vector port for connecting devices")
|
|
||||||
bus_id = Param.Int(0, "blah")
|
|
||||||
clock = Param.Clock("1GHz", "bus clock speed")
|
|
||||||
width = Param.Int(64, "bus width (bytes)")
|
|
||||||
responder_set = Param.Bool(False, "Did the user specify a default responder.")
|
|
||||||
block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
|
|
||||||
if build_env['FULL_SYSTEM']:
|
|
||||||
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
|
|
||||||
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
|
|
||||||
else:
|
|
||||||
default = Port("Default port for requests that aren't handled by a device.")
|
|
|
@ -1,16 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
class DiskImage(SimObject):
|
|
||||||
type = 'DiskImage'
|
|
||||||
abstract = True
|
|
||||||
image_file = Param.String("disk image file")
|
|
||||||
read_only = Param.Bool(False, "read only image")
|
|
||||||
|
|
||||||
class RawDiskImage(DiskImage):
|
|
||||||
type = 'RawDiskImage'
|
|
||||||
|
|
||||||
class CowDiskImage(DiskImage):
|
|
||||||
type = 'CowDiskImage'
|
|
||||||
child = Param.DiskImage(RawDiskImage(read_only=True),
|
|
||||||
"child image")
|
|
||||||
table_size = Param.Int(65536, "initial table size")
|
|
|
@ -1,12 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from FuncUnit import *
|
|
||||||
from FuncUnitConfig import *
|
|
||||||
|
|
||||||
class FUPool(SimObject):
|
|
||||||
type = 'FUPool'
|
|
||||||
FUList = VectorParam.FUDesc("list of FU's for this pool")
|
|
||||||
|
|
||||||
class DefaultFUPool(FUPool):
|
|
||||||
FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
|
|
||||||
WritePort(), RdWrPort(), IprPort() ]
|
|
|
@ -1,18 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
|
|
||||||
class OpType(Enum):
|
|
||||||
vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
|
|
||||||
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
|
|
||||||
'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
|
|
||||||
|
|
||||||
class OpDesc(SimObject):
|
|
||||||
type = 'OpDesc'
|
|
||||||
issueLat = Param.Int(1, "cycles until another can be issued")
|
|
||||||
opClass = Param.OpType("type of operation")
|
|
||||||
opLat = Param.Int(1, "cycles until result is available")
|
|
||||||
|
|
||||||
class FUDesc(SimObject):
|
|
||||||
type = 'FUDesc'
|
|
||||||
count = Param.Int("number of these FU's available")
|
|
||||||
opList = VectorParam.OpDesc("operation classes for this FU type")
|
|
|
@ -1,41 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from FuncUnit import *
|
|
||||||
|
|
||||||
class IntALU(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='IntAlu') ]
|
|
||||||
count = 6
|
|
||||||
|
|
||||||
class IntMultDiv(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='IntMult', opLat=3),
|
|
||||||
OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
|
|
||||||
count=2
|
|
||||||
|
|
||||||
class FP_ALU(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='FloatAdd', opLat=2),
|
|
||||||
OpDesc(opClass='FloatCmp', opLat=2),
|
|
||||||
OpDesc(opClass='FloatCvt', opLat=2) ]
|
|
||||||
count = 4
|
|
||||||
|
|
||||||
class FP_MultDiv(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='FloatMult', opLat=4),
|
|
||||||
OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
|
|
||||||
OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
|
|
||||||
count = 2
|
|
||||||
|
|
||||||
class ReadPort(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='MemRead') ]
|
|
||||||
count = 0
|
|
||||||
|
|
||||||
class WritePort(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='MemWrite') ]
|
|
||||||
count = 0
|
|
||||||
|
|
||||||
class RdWrPort(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
|
|
||||||
count = 4
|
|
||||||
|
|
||||||
class IprPort(FUDesc):
|
|
||||||
opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
|
|
||||||
count = 1
|
|
||||||
|
|
|
@ -1,40 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from Pci import PciDevice, PciConfigData
|
|
||||||
|
|
||||||
class IdeID(Enum): vals = ['master', 'slave']
|
|
||||||
|
|
||||||
class IdeControllerPciData(PciConfigData):
|
|
||||||
VendorID = 0x8086
|
|
||||||
DeviceID = 0x7111
|
|
||||||
Command = 0x0
|
|
||||||
Status = 0x280
|
|
||||||
Revision = 0x0
|
|
||||||
ClassCode = 0x01
|
|
||||||
SubClassCode = 0x01
|
|
||||||
ProgIF = 0x85
|
|
||||||
BAR0 = 0x00000001
|
|
||||||
BAR1 = 0x00000001
|
|
||||||
BAR2 = 0x00000001
|
|
||||||
BAR3 = 0x00000001
|
|
||||||
BAR4 = 0x00000001
|
|
||||||
BAR5 = 0x00000001
|
|
||||||
InterruptLine = 0x1f
|
|
||||||
InterruptPin = 0x01
|
|
||||||
BAR0Size = '8B'
|
|
||||||
BAR1Size = '4B'
|
|
||||||
BAR2Size = '8B'
|
|
||||||
BAR3Size = '4B'
|
|
||||||
BAR4Size = '16B'
|
|
||||||
|
|
||||||
class IdeDisk(SimObject):
|
|
||||||
type = 'IdeDisk'
|
|
||||||
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
|
|
||||||
driveID = Param.IdeID('master', "Drive ID")
|
|
||||||
image = Param.DiskImage("Disk image")
|
|
||||||
|
|
||||||
class IdeController(PciDevice):
|
|
||||||
type = 'IdeController'
|
|
||||||
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
|
|
||||||
|
|
||||||
configdata =IdeControllerPciData()
|
|
|
@ -1,6 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
class IntrControl(SimObject):
|
|
||||||
type = 'IntrControl'
|
|
||||||
sys = Param.System(Parent.any, "the system we are part of")
|
|
|
@ -1,6 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.SimObject import SimObject
|
|
||||||
|
|
||||||
class MemObject(SimObject):
|
|
||||||
type = 'MemObject'
|
|
||||||
abstract = True
|
|
|
@ -1,24 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from m5 import build_env
|
|
||||||
|
|
||||||
class MemTest(SimObject):
|
|
||||||
type = 'MemTest'
|
|
||||||
max_loads = Param.Counter("number of loads to execute")
|
|
||||||
atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
|
|
||||||
memory_size = Param.Int(65536, "memory size")
|
|
||||||
percent_dest_unaligned = Param.Percent(50,
|
|
||||||
"percent of copy dest address that are unaligned")
|
|
||||||
percent_reads = Param.Percent(65, "target read percentage")
|
|
||||||
percent_source_unaligned = Param.Percent(50,
|
|
||||||
"percent of copy source address that are unaligned")
|
|
||||||
percent_functional = Param.Percent(50, "percent of access that are functional")
|
|
||||||
percent_uncacheable = Param.Percent(10,
|
|
||||||
"target uncacheable percentage")
|
|
||||||
progress_interval = Param.Counter(1000000,
|
|
||||||
"progress report interval (in accesses)")
|
|
||||||
trace_addr = Param.Addr(0, "address to trace")
|
|
||||||
|
|
||||||
test = Port("Port to the memory system to test")
|
|
||||||
functional = Port("Port to the functional memory used for verification")
|
|
|
@ -1,29 +0,0 @@
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from MemObject import *
|
|
||||||
|
|
||||||
class PhysicalMemory(MemObject):
|
|
||||||
type = 'PhysicalMemory'
|
|
||||||
port = VectorPort("the access port")
|
|
||||||
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
|
|
||||||
file = Param.String('', "memory mapped file")
|
|
||||||
latency = Param.Latency('1t', "latency of an access")
|
|
||||||
zero = Param.Bool(False, "zero initialize memory")
|
|
||||||
|
|
||||||
class DRAMMemory(PhysicalMemory):
|
|
||||||
type = 'DRAMMemory'
|
|
||||||
# Many of these should be observed from the configuration
|
|
||||||
cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
|
|
||||||
mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
|
|
||||||
mem_actpolicy = Param.String("open", "Open/Close policy")
|
|
||||||
memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
|
|
||||||
bus_width = Param.Int(16, "")
|
|
||||||
act_lat = Param.Int(2, "RAS to CAS delay")
|
|
||||||
cas_lat = Param.Int(1, "CAS delay")
|
|
||||||
war_lat = Param.Int(2, "write after read delay")
|
|
||||||
pre_lat = Param.Int(2, "precharge delay")
|
|
||||||
dpl_lat = Param.Int(2, "data in to precharge delay")
|
|
||||||
trc_lat = Param.Int(6, "row cycle delay")
|
|
||||||
num_banks = Param.Int(4, "Number of Banks")
|
|
||||||
num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
|
|
||||||
|
|
|
@ -1,7 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
class Platform(SimObject):
|
|
||||||
type = 'Platform'
|
|
||||||
abstract = True
|
|
||||||
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
|
|
|
@ -1,36 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
class Process(SimObject):
|
|
||||||
type = 'Process'
|
|
||||||
abstract = True
|
|
||||||
output = Param.String('cout', 'filename for stdout/stderr')
|
|
||||||
system = Param.System(Parent.any, "system process will run on")
|
|
||||||
|
|
||||||
class LiveProcess(Process):
|
|
||||||
type = 'LiveProcess'
|
|
||||||
executable = Param.String('', "executable (overrides cmd[0] if set)")
|
|
||||||
cmd = VectorParam.String("command line (executable plus arguments)")
|
|
||||||
env = VectorParam.String('', "environment settings")
|
|
||||||
cwd = Param.String('', "current working directory")
|
|
||||||
input = Param.String('cin', "filename for stdin")
|
|
||||||
uid = Param.Int(100, 'user id')
|
|
||||||
euid = Param.Int(100, 'effective user id')
|
|
||||||
gid = Param.Int(100, 'group id')
|
|
||||||
egid = Param.Int(100, 'effective group id')
|
|
||||||
pid = Param.Int(100, 'process id')
|
|
||||||
ppid = Param.Int(99, 'parent process id')
|
|
||||||
|
|
||||||
class AlphaLiveProcess(LiveProcess):
|
|
||||||
type = 'AlphaLiveProcess'
|
|
||||||
|
|
||||||
class SparcLiveProcess(LiveProcess):
|
|
||||||
type = 'SparcLiveProcess'
|
|
||||||
|
|
||||||
class MipsLiveProcess(LiveProcess):
|
|
||||||
type = 'MipsLiveProcess'
|
|
||||||
|
|
||||||
class EioProcess(Process):
|
|
||||||
type = 'EioProcess'
|
|
||||||
chkpt = Param.String('', "EIO checkpoint file name (optional)")
|
|
||||||
file = Param.String("EIO trace file name")
|
|
|
@ -1,6 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
|
|
||||||
class Root(SimObject):
|
|
||||||
type = 'Root'
|
|
||||||
dummy = Param.Int(0, "We don't support objects without params")
|
|
|
@ -1,11 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
|
|
||||||
class SimConsole(SimObject):
|
|
||||||
type = 'SimConsole'
|
|
||||||
append_name = Param.Bool(True, "append name() to filename")
|
|
||||||
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
|
|
||||||
port = Param.TcpPort(3456, "listen port")
|
|
||||||
number = Param.Int(0, "console number")
|
|
||||||
output = Param.String('console', "file to dump output to")
|
|
|
@ -1,7 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
class SimpleDisk(SimObject):
|
|
||||||
type = 'SimpleDisk'
|
|
||||||
disk = Param.DiskImage("Disk Image")
|
|
||||||
system = Param.System(Parent.any, "Sysetm Pointer")
|
|
|
@ -1,14 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
class SparcTLB(SimObject):
|
|
||||||
type = 'SparcTLB'
|
|
||||||
abstract = True
|
|
||||||
size = Param.Int("TLB size")
|
|
||||||
|
|
||||||
class SparcDTB(SparcTLB):
|
|
||||||
type = 'SparcDTB'
|
|
||||||
size = 64
|
|
||||||
|
|
||||||
class SparcITB(SparcTLB):
|
|
||||||
type = 'SparcITB'
|
|
||||||
size = 64
|
|
|
@ -1,68 +0,0 @@
|
||||||
from m5.SimObject import SimObject
|
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from m5 import build_env
|
|
||||||
from PhysicalMemory import *
|
|
||||||
|
|
||||||
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
|
|
||||||
|
|
||||||
class System(SimObject):
|
|
||||||
type = 'System'
|
|
||||||
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
|
|
||||||
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
|
|
||||||
if build_env['FULL_SYSTEM']:
|
|
||||||
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
|
|
||||||
"boot processor frequency")
|
|
||||||
init_param = Param.UInt64(0, "numerical value to pass into simulator")
|
|
||||||
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
|
|
||||||
kernel = Param.String("", "file that contains the kernel code")
|
|
||||||
readfile = Param.String("", "file to read startup script from")
|
|
||||||
symbolfile = Param.String("", "file to get the symbols from")
|
|
||||||
|
|
||||||
class AlphaSystem(System):
|
|
||||||
type = 'AlphaSystem'
|
|
||||||
console = Param.String("file that contains the console code")
|
|
||||||
pal = Param.String("file that contains palcode")
|
|
||||||
system_type = Param.UInt64("Type of system we are emulating")
|
|
||||||
system_rev = Param.UInt64("Revision of system we are emulating")
|
|
||||||
|
|
||||||
class SparcSystem(System):
|
|
||||||
type = 'SparcSystem'
|
|
||||||
_rom_base = 0xfff0000000
|
|
||||||
_nvram_base = 0x1f11000000
|
|
||||||
_hypervisor_desc_base = 0x1f12080000
|
|
||||||
_partition_desc_base = 0x1f12000000
|
|
||||||
# ROM for OBP/Reset/Hypervisor
|
|
||||||
rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')),
|
|
||||||
"Memory to hold the ROM data")
|
|
||||||
# nvram
|
|
||||||
nvram = Param.PhysicalMemory(
|
|
||||||
PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')),
|
|
||||||
"Memory to hold the nvram data")
|
|
||||||
# hypervisor description
|
|
||||||
hypervisor_desc = Param.PhysicalMemory(
|
|
||||||
PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')),
|
|
||||||
"Memory to hold the hypervisor description")
|
|
||||||
# partition description
|
|
||||||
partition_desc = Param.PhysicalMemory(
|
|
||||||
PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')),
|
|
||||||
"Memory to hold the partition description")
|
|
||||||
|
|
||||||
reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
|
|
||||||
hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
|
|
||||||
"Address to load hypervisor at")
|
|
||||||
openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
|
|
||||||
"Address to load openboot at")
|
|
||||||
nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
|
|
||||||
hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
|
|
||||||
"Address for the hypervisor description")
|
|
||||||
partition_desc_addr = Param.Addr(_partition_desc_base,
|
|
||||||
"Address for the partition description")
|
|
||||||
|
|
||||||
reset_bin = Param.String("file that contains the reset code")
|
|
||||||
hypervisor_bin = Param.String("file that contains the hypervisor code")
|
|
||||||
openboot_bin = Param.String("file that contains the openboot code")
|
|
||||||
nvram_bin = Param.String("file that contains the contents of nvram")
|
|
||||||
hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
|
|
||||||
partition_desc_bin = Param.String("file that contains the partition description")
|
|
||||||
|
|
|
@ -1,17 +0,0 @@
|
||||||
from m5.params import *
|
|
||||||
from m5.proxy import *
|
|
||||||
from m5 import build_env
|
|
||||||
from Device import BasicPioDevice
|
|
||||||
|
|
||||||
class Uart(BasicPioDevice):
|
|
||||||
type = 'Uart'
|
|
||||||
abstract = True
|
|
||||||
sim_console = Param.SimConsole(Parent.any, "The console")
|
|
||||||
|
|
||||||
class Uart8250(Uart):
|
|
||||||
type = 'Uart8250'
|
|
||||||
|
|
||||||
if build_env['ALPHA_TLASER']:
|
|
||||||
class Uart8530(Uart):
|
|
||||||
type = 'Uart8530'
|
|
||||||
|
|
51
src/sim/Process.py
Normal file
51
src/sim/Process.py
Normal file
|
@ -0,0 +1,51 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
|
||||||
|
class Process(SimObject):
|
||||||
|
type = 'Process'
|
||||||
|
abstract = True
|
||||||
|
output = Param.String('cout', 'filename for stdout/stderr')
|
||||||
|
system = Param.System(Parent.any, "system process will run on")
|
||||||
|
|
||||||
|
class LiveProcess(Process):
|
||||||
|
type = 'LiveProcess'
|
||||||
|
executable = Param.String('', "executable (overrides cmd[0] if set)")
|
||||||
|
cmd = VectorParam.String("command line (executable plus arguments)")
|
||||||
|
env = VectorParam.String('', "environment settings")
|
||||||
|
cwd = Param.String('', "current working directory")
|
||||||
|
input = Param.String('cin', "filename for stdin")
|
||||||
|
uid = Param.Int(100, 'user id')
|
||||||
|
euid = Param.Int(100, 'effective user id')
|
||||||
|
gid = Param.Int(100, 'group id')
|
||||||
|
egid = Param.Int(100, 'effective group id')
|
||||||
|
pid = Param.Int(100, 'process id')
|
||||||
|
ppid = Param.Int(99, 'parent process id')
|
34
src/sim/Root.py
Normal file
34
src/sim/Root.py
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
|
||||||
|
class Root(SimObject):
|
||||||
|
type = 'Root'
|
||||||
|
dummy = Param.Int(0, "We don't support objects without params")
|
|
@ -30,6 +30,9 @@
|
||||||
|
|
||||||
Import('*')
|
Import('*')
|
||||||
|
|
||||||
|
SimObject('Root.py')
|
||||||
|
SimObject('System.py')
|
||||||
|
|
||||||
Source('async.cc')
|
Source('async.cc')
|
||||||
Source('builder.cc')
|
Source('builder.cc')
|
||||||
Source('core.cc')
|
Source('core.cc')
|
||||||
|
@ -50,5 +53,7 @@ Source('system.cc')
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
Source('pseudo_inst.cc')
|
Source('pseudo_inst.cc')
|
||||||
else:
|
else:
|
||||||
|
SimObject('Process.py')
|
||||||
|
|
||||||
Source('process.cc')
|
Source('process.cc')
|
||||||
Source('syscall_emul.cc')
|
Source('syscall_emul.cc')
|
||||||
|
|
48
src/sim/System.py
Normal file
48
src/sim/System.py
Normal file
|
@ -0,0 +1,48 @@
|
||||||
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Nathan Binkert
|
||||||
|
|
||||||
|
from m5.SimObject import SimObject
|
||||||
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
|
from m5 import build_env
|
||||||
|
from PhysicalMemory import *
|
||||||
|
|
||||||
|
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
|
||||||
|
|
||||||
|
class System(SimObject):
|
||||||
|
type = 'System'
|
||||||
|
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
|
||||||
|
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
|
||||||
|
"boot processor frequency")
|
||||||
|
init_param = Param.UInt64(0, "numerical value to pass into simulator")
|
||||||
|
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
|
||||||
|
kernel = Param.String("", "file that contains the kernel code")
|
||||||
|
readfile = Param.String("", "file to read startup script from")
|
||||||
|
symbolfile = Param.String("", "file to get the symbols from")
|
Loading…
Reference in a new issue