sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

X86: Don't fetch in the simple CPU if you're in the ROM.

Browse source
This commit is contained in:
Gabe Black 2008-10-12 19:32:06 -07:00
parent f245358343
commit 0756dbb37a
2 changed files with 56 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/cpu/simple/atomic.cc
View file

@ -718,13 +718,18 @@ AtomicSimpleCPU::tick()
checkPcEventQueue();
Fault fault = setupFetchRequest(&ifetch_req);
Fault fault = NoFault;
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom)
fault = setupFetchRequest(&ifetch_req);
if (fault == NoFault) {
Tick icache_latency = 0;
bool icache_access = false;
dcache_access = false; // assume no dcache access
if (!fromRom) {
//Fetch more instruction memory if necessary
//if(predecoder.needMoreBytes())
//{
@ -743,6 +748,7 @@ AtomicSimpleCPU::tick()
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
//}
}
preExecute();

14
src/cpu/simple/timing.cc
View file

@ -531,6 +531,9 @@ TimingSimpleCPU::fetch()
checkPcEventQueue();
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom) {
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);
@ -554,6 +557,10 @@ TimingSimpleCPU::fetch()
// fetch fault: advance directly to next instruction (fault handler)
advanceInst(fault);
}
} else {
_status = IcacheWaitResponse;
completeIfetch(NULL);
}
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@ -581,7 +588,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
// received a response from the icache: execute the received
// instruction
assert(!pkt->isError());
assert(!pkt || !pkt->isError());
assert(_status == IcacheWaitResponse);
_status = Running;
@ -590,8 +598,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
previousTick = curTick;
if (getState() == SimObject::Draining) {
if (pkt) {
delete pkt->req;
delete pkt;
}
completeDrain();
return;
@ -658,8 +668,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
advanceInst(fault);
}
if (pkt) {
delete pkt->req;
delete pkt;
}
}
void