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Fix compile issues on gcc 4.1.x related to namespaces.

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This basically involves moving the builder code outside of any
namespace.  While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.

--HG--
extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
This commit is contained in:
Nathan Binkert 2007-02-21 16:42:16 -08:00
parent 2a67f2b08c
commit 06ae2d0445
2 changed files with 16 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/arch/alpha/tlb.cc
View file

@ -46,8 +46,7 @@
using namespace std; using namespace std;
using namespace EV5; using namespace EV5;
namespace AlphaISA namespace AlphaISA {
{
/////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////
// //
// Alpha TLB // Alpha TLB
@ -116,10 +115,11 @@ TLB::checkCacheability(RequestPtr &req)
#if ALPHA_TLASER #if ALPHA_TLASER
if (req->getPaddr() & PAddrUncachedBit39) { if (req->getPaddr() & PAddrUncachedBit39)
#else #else
if (req->getPaddr() & PAddrUncachedBit43) { if (req->getPaddr() & PAddrUncachedBit43)
#endif #endif
{
// IPR memory space not implemented // IPR memory space not implemented
if (PAddrIprSpace(req->getPaddr())) { if (PAddrIprSpace(req->getPaddr())) {
return new UnimpFault("IPR memory space not implemented!"); return new UnimpFault("IPR memory space not implemented!");
@ -313,10 +313,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER #if ALPHA_TLASER
if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) { VAddrSpaceEV5(req->getVaddr()) == 2)
#else #else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
#endif #endif
{
// only valid in kernel mode // only valid in kernel mode
if (ICM_CM(tc->readMiscReg(IPR_ICM)) != if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
mode_kernel) { mode_kernel) {
@ -487,10 +488,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
// Check for "superpage" mapping // Check for "superpage" mapping
#if ALPHA_TLASER #if ALPHA_TLASER
if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) { VAddrSpaceEV5(req->getVaddr()) == 2)
#else #else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
#endif #endif
{
// only valid in kernel mode // only valid in kernel mode
if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
@ -592,6 +594,8 @@ TLB::index(bool advance)
return *pte; return *pte;
} }
/* end namespace AlphaISA */ }
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
@ -633,4 +637,3 @@ CREATE_SIM_OBJECT(DTB)
} }
REGISTER_SIM_OBJECT("AlphaDTB", DTB) REGISTER_SIM_OBJECT("AlphaDTB", DTB)
}

7
src/arch/sparc/tlb.cc
View file

@ -43,8 +43,7 @@
/* @todo remove some of the magic constants. -- ali /* @todo remove some of the magic constants. -- ali
* */ * */
namespace SparcISA namespace SparcISA {
{
TLB::TLB(const std::string &name, int s) TLB::TLB(const std::string &name, int s)
: SimObject(name), size(s), usedEntries(0), lastReplaced(0), : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
@ -1329,6 +1328,9 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
} }
} }
/* end namespace SparcISA */ }
using namespace SparcISA;
DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
@ -1371,4 +1373,3 @@ CREATE_SIM_OBJECT(DTB)
} }
REGISTER_SIM_OBJECT("SparcDTB", DTB) REGISTER_SIM_OBJECT("SparcDTB", DTB)
}