Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 2dfc24b0720b3b378858a289e4bb6f4ee7132b3d
This commit is contained in:
commit
053c715f21
11 changed files with 381 additions and 46 deletions
|
@ -182,6 +182,33 @@ output decoder {{
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ccprintf(os, "\t%s : %s ", instMnemonic, mnemonic);
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}
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void printSegment(std::ostream &os, int segment)
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{
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switch (segment)
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{
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case 0:
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ccprintf(os, "ES");
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break;
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case 1:
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ccprintf(os, "CS");
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break;
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case 2:
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ccprintf(os, "SS");
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break;
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case 3:
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ccprintf(os, "DS");
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break;
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case 4:
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ccprintf(os, "FS");
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break;
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case 5:
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ccprintf(os, "GS");
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break;
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default:
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panic("Unrecognized segment %d\n", segment);
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}
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}
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void
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X86StaticInst::printSrcReg(std::ostream &os, int reg) const
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{
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@ -100,3 +100,8 @@ def bitfield SIB_BASE sib.base;
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def bitfield OPSIZE opSize;
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def bitfield ADDRSIZE addrSize;
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def bitfield STACKSIZE stackSize;
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def bitfield MODE mode;
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def bitfield MODE_MODE mode.mode;
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def bitfield MODE_SUBMODE mode.submode;
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@ -67,11 +67,11 @@ def macroop MOV_R_M {
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};
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def macroop MOV_R_I {
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limm "env.reg", "env.immediate"
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limm "env.reg", "IMMEDIATE"
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};
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def macroop MOV_M_I {
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limm "env.reg", "env.immediate"
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limm "env.reg", "IMMEDIATE"
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#Do a store to put the register operand into memory
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};
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'''
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@ -55,15 +55,21 @@
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microcode = '''
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def macroop POP_R {
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# Make the default data size of pops 64 bits in 64 bit mode
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.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
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# There needs to be a load here to actually "pop" the data
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ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
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addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
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};
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def macroop PUSH_R {
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# Make the default data size of pops 64 bits in 64 bit mode
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.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
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subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
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# There needs to be a store here to actually "push" the data
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st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
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};
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'''
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#let {{
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@ -61,34 +61,34 @@ def macroop XOR_R_R
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def macroop XOR_R_I
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{
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limm "NUM_INTREGS", "env.immediate"
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xor "env.reg", "env.reg", "NUM_INTREGS"
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limm "NUM_INTREGS+1", "IMMEDIATE"
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xor "env.reg", "env.reg", "NUM_INTREGS+1"
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};
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def macroop XOR_M_R
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{
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#Do a load to get one of the sources
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xor "NUM_INTREGS", "NUM_INTREGS", "env.reg"
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xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
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#Do a store to write the destination
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};
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def macroop XOR_R_M
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{
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#Do a load to get one of the sources
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xor "env.reg", "env.reg", "NUM_INTREGS"
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xor "env.reg", "env.reg", "NUM_INTREGS+1"
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};
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def macroop AND_R_I
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{
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limm "NUM_INTREGS", "env.immediate"
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and "env.reg", "env.reg", "NUM_INTREGS"
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limm "NUM_INTREGS+1", "IMMEDIATE"
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and "env.reg", "env.reg", "NUM_INTREGS+1"
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};
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def macroop AND_M_I
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{
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#Do a load to get one of the sources
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limm "NUM_INTREGS", "env.immediate"
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and "NUM_INTREGS", "NUM_INTREGS", "NUM_INTREGS+1"
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limm "NUM_INTREGS+1", "IMMEDIATE"
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and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2"
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#Do a store to write the destination
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};
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'''
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@ -189,17 +189,18 @@ output header {{
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{
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X86ISA::RegIndex reg;
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X86ISA::RegIndex regm;
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uint64_t immediate;
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uint64_t displacement;
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int addressSize;
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uint8_t scale;
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X86ISA::RegIndex index;
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X86ISA::RegIndex base;
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int dataSize;
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int addressSize;
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int stackSize;
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EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm,
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uint64_t _immediate, uint64_t _displacement,
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int _addressSize, int _dataSize) :
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int _dataSize, int _addressSize, int _stackSize) :
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reg(_reg), regm(_regm),
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immediate(_immediate), displacement(_displacement),
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addressSize(_addressSize), dataSize(_dataSize)
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dataSize(_dataSize), addressSize(_addressSize),
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stackSize(_stackSize)
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{;}
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};
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}};
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@ -211,17 +212,15 @@ let {{
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self.regUsed = False
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self.regm = "0"
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self.regmUsed = False
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self.immediate = "IMMEDIATE"
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self.displacement = "DISPLACEMENT"
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self.addressSize = "ADDRSIZE"
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self.dataSize = "OPSIZE"
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self.stackSize = "STACKSIZE"
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def getAllocator(self):
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return '''EmulEnv(%(reg)s,
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%(regm)s,
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%(immediate)s,
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%(displacement)s,
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%(dataSize)s,
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%(addressSize)s,
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%(dataSize)s)''' % \
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%(stackSize)s)''' % \
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self.__dict__
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def addReg(self, reg):
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if not self.regUsed:
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@ -59,8 +59,14 @@
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//
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//////////////////////////////////////////////////////////////////////////
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def template MicroLdStOpDeclare {{
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class %(class_name)s : public X86MicroopBase
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// Load templates
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output header {{
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/**
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* Base class for load and store ops
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*/
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class LdStOp : public X86MicroopBase
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{
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protected:
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const uint8_t scale;
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@ -71,6 +77,195 @@ def template MicroLdStOpDeclare {{
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const RegIndex data;
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const uint8_t dataSize;
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const uint8_t addressSize;
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//Constructor
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LdStOp(ExtMachInst _machInst,
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const char * mnem, const char * _instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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OpClass __opClass) :
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X86MicroopBase(machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast, __opClass),
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scale(_scale), index(_index), base(_base),
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disp(_disp), segment(_segment),
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data(_data),
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dataSize(_dataSize), addressSize(_addressSize)
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string LdStOp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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printReg(response, data);
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response << ", ";
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printSegment(response, segment);
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ccprintf(response, ":[%d*", scale);
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printReg(response, index);
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response << " + ";
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printReg(response, base);
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ccprintf(response, " + %#x]", disp);
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return response.str();
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}
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}};
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def template MicroLoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0);
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if(fault == NoFault)
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{
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%(code)s;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0);
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return fault;
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}
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}};
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def template MicroLoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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Mem = pkt->get<typeof(Mem)>();
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Store templates
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def template MicroStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s * xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
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EA, 0, 0);
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroStoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
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EA, 0, 0);
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}
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if(fault == NoFault)
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{
|
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%(op_wb)s;
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}
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return fault;
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}
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}};
|
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def template MicroStoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
|
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Trace::InstRecord * traceData) const
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{
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return NoFault;
|
||||
}
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}};
|
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|
||||
// Common templates
|
||||
|
||||
//This delcares the initiateAcc function in memory operations
|
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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|
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//This declares the completeAcc function in memory operations
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
|
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|
||||
def template MicroLdStOpDeclare {{
|
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class %(class_name)s : public %(base_class)s
|
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{
|
||||
protected:
|
||||
void buildMe();
|
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|
||||
public:
|
||||
|
@ -90,6 +285,10 @@ def template MicroLdStOpDeclare {{
|
|||
uint8_t _dataSize, uint8_t _addressSize);
|
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|
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%(BasicExecDeclare)s
|
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|
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%(InitiateAccDeclare)s
|
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|
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%(CompleteAccDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
|
@ -107,11 +306,10 @@ def template MicroLdStOpConstructor {{
|
|||
RegIndex _data,
|
||||
uint8_t _dataSize, uint8_t _addressSize) :
|
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
|
||||
false, false, false, false, %(op_class)s),
|
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scale(_scale), index(_index), base(_base),
|
||||
disp(_disp), segment(_segment),
|
||||
data(_data),
|
||||
dataSize(_dataSize), addressSize(_addressSize)
|
||||
false, false, false, false,
|
||||
_scale, _index, _base,
|
||||
_disp, _segment, _data,
|
||||
_dataSize, _addressSize, %(op_class)s)
|
||||
{
|
||||
buildMe();
|
||||
}
|
||||
|
@ -120,17 +318,106 @@ def template MicroLdStOpConstructor {{
|
|||
ExtMachInst machInst, const char * instMnem,
|
||||
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
|
||||
uint8_t _scale, RegIndex _index, RegIndex _base,
|
||||
uint64_t _disp, uint8_t segment,
|
||||
RegIndex data,
|
||||
uint8_t dataSize, uint8_t addressSize) :
|
||||
uint64_t _disp, uint8_t _segment,
|
||||
RegIndex _data,
|
||||
uint8_t _dataSize, uint8_t _addressSize) :
|
||||
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
|
||||
isMicro, isDelayed, isFirst, isLast, %(op_class)s),
|
||||
scale(_scale), index(_index), base(_base),
|
||||
disp(_disp), segment(_segment),
|
||||
data(_data),
|
||||
dataSize(_dataSize), addressSize(_addressSize)
|
||||
isMicro, isDelayed, isFirst, isLast,
|
||||
_scale, _index, _base,
|
||||
_disp, _segment, _data,
|
||||
_dataSize, _addressSize, %(op_class)s)
|
||||
{
|
||||
buildMe();
|
||||
}
|
||||
}};
|
||||
|
||||
let {{
|
||||
class LdStOp(X86Microop):
|
||||
def __init__(self, data, segment, addr, disp):
|
||||
self.data = data
|
||||
[self.scale, self.index, self.base] = addr
|
||||
self.disp = disp
|
||||
self.segment = segment
|
||||
self.dataSize = "env.dataSize"
|
||||
self.addressSize = "env.addressSize"
|
||||
|
||||
def getAllocator(self, *microFlags):
|
||||
allocator = '''new %(class_name)s(machInst, mnemonic
|
||||
%(flags)s, %(scale)s, %(index)s, %(base)s,
|
||||
%(disp)s, %(segment)s, %(data)s,
|
||||
%(dataSize)s, %(addressSize)s)''' % {
|
||||
"class_name" : self.className,
|
||||
"flags" : self.microFlagsText(microFlags),
|
||||
"scale" : self.scale, "index" : self.index,
|
||||
"base" : self.base,
|
||||
"disp" : self.disp,
|
||||
"segment" : self.segment, "data" : self.data,
|
||||
"dataSize" : self.dataSize, "addressSize" : self.addressSize}
|
||||
return allocator
|
||||
}};
|
||||
|
||||
let {{
|
||||
|
||||
# Make these empty strings so that concatenating onto
|
||||
# them will always work.
|
||||
header_output = ""
|
||||
decoder_output = ""
|
||||
exec_output = ""
|
||||
|
||||
calculateEA = "EA = scale * Index + Base + disp;"
|
||||
|
||||
def defineMicroLoadOp(mnemonic, code):
|
||||
global header_output
|
||||
global decoder_output
|
||||
global exec_output
|
||||
global microopClasses
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
|
||||
# Build up the all register version of this micro op
|
||||
iop = InstObjParams(name, Name, 'LdStOp',
|
||||
{"code": code, "ea_code": calculateEA})
|
||||
header_output += MicroLdStOpDeclare.subst(iop)
|
||||
decoder_output += MicroLdStOpConstructor.subst(iop)
|
||||
exec_output += MicroLoadExecute.subst(iop)
|
||||
exec_output += MicroLoadInitiateAcc.subst(iop)
|
||||
exec_output += MicroLoadCompleteAcc.subst(iop)
|
||||
|
||||
class LoadOp(LdStOp):
|
||||
def __init__(self, data, segment, addr, disp = 0):
|
||||
super(LoadOp, self).__init__(data, segment, addr, disp)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
microopClasses[name] = LoadOp
|
||||
|
||||
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
|
||||
|
||||
def defineMicroStoreOp(mnemonic, code):
|
||||
global header_output
|
||||
global decoder_output
|
||||
global exec_output
|
||||
global microopClasses
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
|
||||
# Build up the all register version of this micro op
|
||||
iop = InstObjParams(name, Name, 'LdStOp',
|
||||
{"code": code, "ea_code": calculateEA})
|
||||
header_output += MicroLdStOpDeclare.subst(iop)
|
||||
decoder_output += MicroLdStOpConstructor.subst(iop)
|
||||
exec_output += MicroStoreExecute.subst(iop)
|
||||
exec_output += MicroStoreInitiateAcc.subst(iop)
|
||||
exec_output += MicroStoreCompleteAcc.subst(iop)
|
||||
|
||||
class StoreOp(LdStOp):
|
||||
def __init__(self, data, addr, segment):
|
||||
super(LoadOp, self).__init__(data, addr, segment)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
microopClasses[name] = StoreOp
|
||||
|
||||
defineMicroLoadOp('St', 'Mem = Data;')
|
||||
}};
|
||||
|
||||
|
|
|
@ -99,7 +99,9 @@ def operands {{
|
|||
'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
|
||||
'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
|
||||
'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
|
||||
'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1),
|
||||
'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2),
|
||||
'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2),
|
||||
'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
|
||||
'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
|
||||
'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
|
||||
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
|
||||
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
|
||||
}};
|
||||
|
|
|
@ -93,7 +93,7 @@ namespace X86ISA
|
|||
|
||||
// semantically meaningful register indices
|
||||
//There is no such register in X86
|
||||
const int ZeroReg = 0;
|
||||
const int ZeroReg = NUM_INTREGS;
|
||||
const int StackPointerReg = INTREG_RSP;
|
||||
//X86 doesn't seem to have a link register
|
||||
const int ReturnAddressReg = 0;
|
||||
|
|
|
@ -169,6 +169,8 @@ namespace X86ISA
|
|||
uint8_t opSize;
|
||||
//The effective address size.
|
||||
uint8_t addrSize;
|
||||
//The effective stack size.
|
||||
uint8_t stackSize;
|
||||
|
||||
//Mode information
|
||||
OperatingMode mode;
|
||||
|
@ -193,8 +195,6 @@ namespace X86ISA
|
|||
inline static bool
|
||||
operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
|
||||
{
|
||||
if(emi1.mode != emi2.mode)
|
||||
return false;
|
||||
if(emi1.legacy != emi2.legacy)
|
||||
return false;
|
||||
if(emi1.rex != emi2.rex)
|
||||
|
@ -215,6 +215,14 @@ namespace X86ISA
|
|||
return false;
|
||||
if(emi1.displacement != emi2.displacement)
|
||||
return false;
|
||||
if(emi1.mode != emi2.mode)
|
||||
return false;
|
||||
if(emi1.opSize != emi2.opSize)
|
||||
return false;
|
||||
if(emi1.addrSize != emi2.addrSize)
|
||||
return false;
|
||||
if(emi1.stackSize != emi2.stackSize)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
@ -79,7 +79,8 @@ namespace __hash_namespace {
|
|||
((uint64_t)emi.opcode.prefixB << 8) |
|
||||
((uint64_t)emi.opcode.op)) ^
|
||||
emi.immediate ^ emi.displacement ^
|
||||
emi.mode ^ emi.opSize;
|
||||
emi.mode ^
|
||||
emi.opSize ^ emi.addrSize ^ emi.stackSize;
|
||||
};
|
||||
};
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue