diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 8b724209e..328e1c7cc 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -135,7 +135,7 @@ BaseCache::CachePort::recvRetry()
     else if (!isCpuSide)
     {
         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
-        if (cache->doMasterRequest()) {
+        if (!cache->doMasterRequest()) {
             //This can happen if I am the owner of a block and see an upgrade
             //while the block was in my WB Buffers.  I just remove the
             //wb and de-assert the masterRequest
@@ -243,7 +243,7 @@ BaseCache::CacheEvent::process()
         else if (!cachePort->isCpuSide)
         {            //MSHR
             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
-            if (cachePort->cache->doMasterRequest()) {
+            if (!cachePort->cache->doMasterRequest()) {
                 //This can happen if I am the owner of a block and see an upgrade
                 //while the block was in my WB Buffers.  I just remove the
                 //wb and de-assert the masterRequest