Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
This commit is contained in:
commit
047f77102b
21 changed files with 353 additions and 148 deletions
|
@ -728,8 +728,10 @@ decode OPCODE default Unknown::unknown() {
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0: OpcdecFault::hw_st_quad();
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1: decode HW_LDST_QUAD {
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format HwLoad {
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0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
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1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
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0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
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L, IsSerializing, IsSerializeBefore);
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1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
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Q, IsSerializing, IsSerializeBefore);
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}
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}
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}
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@ -740,9 +742,9 @@ decode OPCODE default Unknown::unknown() {
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1: decode HW_LDST_COND {
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0: decode HW_LDST_QUAD {
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0: hw_st({{ EA = (Rb + disp) & ~3; }},
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{{ Mem.ul = Ra<31:0>; }}, L);
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{{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
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1: hw_st({{ EA = (Rb + disp) & ~7; }},
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{{ Mem.uq = Ra.uq; }}, Q);
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{{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
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}
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1: FailUnimpl::hw_st_cond();
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@ -226,7 +226,8 @@ BaseCPU::startup()
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#endif
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if (params->progress_interval) {
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new CPUProgressEvent(&mainEventQueue, params->progress_interval,
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new CPUProgressEvent(&mainEventQueue,
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cycles(params->progress_interval),
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this);
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}
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}
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@ -171,15 +171,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** The memory request. */
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Request *req;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** Is the effective virtual address valid. */
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bool effAddrValid;
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/** The effective physical address. */
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Addr physEffAddr;
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@ -601,12 +601,18 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns whether or not this instruction is ready to issue. */
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bool readyToIssue() const { return status[CanIssue]; }
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/** Clears this instruction being able to issue. */
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void clearCanIssue() { status.reset(CanIssue); }
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/** Sets this instruction as issued from the IQ. */
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void setIssued() { status.set(Issued); }
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/** Returns whether or not this instruction has issued. */
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bool isIssued() const { return status[Issued]; }
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/** Clears this instruction as being issued. */
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void clearIssued() { status.reset(Issued); }
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/** Sets this instruction as executed. */
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void setExecuted() { status.set(Executed); }
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@ -729,6 +735,12 @@ class BaseDynInst : public FastAlloc, public RefCounted
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*/
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bool eaCalcDone;
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/** Is this instruction's memory access uncacheable. */
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bool isUncacheable;
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/** Has this instruction generated a memory request. */
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bool reqMade;
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public:
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/** Sets the effective address. */
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void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
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@ -745,6 +757,12 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Whether or not the memory operation is done. */
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bool memOpDone;
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/** Is this instruction's memory access uncacheable. */
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bool uncacheable() { return isUncacheable; }
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/** Has this instruction generated a memory request. */
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bool hasRequest() { return reqMade; }
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public:
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/** Load queue index. */
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int16_t lqIdx;
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@ -776,25 +794,25 @@ template<class T>
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inline Fault
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BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
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{
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// Sometimes reads will get retried, so they may come through here
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// twice.
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if (!req) {
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req = new Request();
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reqMade = true;
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Request *req = new Request();
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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} else {
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assert(addr == req->getVaddr());
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}
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if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
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TheISA::VMPageSize) {
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delete req;
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return TheISA::genAlignmentFault();
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}
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fault = cpu->translateDataReadReq(req, thread);
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if (req->isUncacheable())
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isUncacheable = true;
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if (fault == NoFault) {
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effAddr = req->getVaddr();
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effAddrValid = true;
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physEffAddr = req->getPaddr();
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memReqFlags = req->getFlags();
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@ -817,6 +835,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
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// Commit will have to clean up whatever happened. Set this
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// instruction as executed.
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this->setExecuted();
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delete req;
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}
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if (traceData) {
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@ -837,21 +856,25 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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traceData->setData(data);
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}
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assert(req == NULL);
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req = new Request();
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reqMade = true;
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Request *req = new Request();
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req->setVirt(asid, addr, sizeof(T), flags, this->PC);
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req->setThreadContext(thread->readCpuId(), threadNumber);
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if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
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TheISA::VMPageSize) {
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delete req;
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return TheISA::genAlignmentFault();
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}
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fault = cpu->translateDataWriteReq(req, thread);
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if (req->isUncacheable())
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isUncacheable = true;
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if (fault == NoFault) {
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effAddr = req->getVaddr();
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effAddrValid = true;
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physEffAddr = req->getPaddr();
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memReqFlags = req->getFlags();
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#if 0
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@ -863,12 +886,8 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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#else
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fault = cpu->write(req, data, sqIdx);
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#endif
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}
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if (res) {
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// always return some result to keep misspeculated paths
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// (which will ignore faults) deterministic
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*res = (fault == NoFault) ? req->getExtraData() : 0;
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} else {
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delete req;
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}
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return fault;
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@ -92,11 +92,13 @@ template <class Impl>
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void
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BaseDynInst<Impl>::initVars()
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{
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req = NULL;
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memData = NULL;
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effAddr = 0;
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effAddrValid = false;
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physEffAddr = 0;
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isUncacheable = false;
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reqMade = false;
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readyRegs = 0;
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instResult.integer = 0;
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@ -140,10 +142,6 @@ BaseDynInst<Impl>::initVars()
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template <class Impl>
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BaseDynInst<Impl>::~BaseDynInst()
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{
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if (req) {
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delete req;
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}
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if (memData) {
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delete [] memData;
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}
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@ -271,7 +269,7 @@ void
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BaseDynInst<Impl>::markSrcRegReady()
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{
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if (++readyRegs == numSrcRegs()) {
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status.set(CanIssue);
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setCanIssue();
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}
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}
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@ -50,11 +50,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
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Param<int> clock;
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Param<int> phase;
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Param<int> numThreads;
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Param<int> cpu_id;
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Param<int> activity;
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#if FULL_SYSTEM
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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SimObjectParam<AlphaISA::ITB *> itb;
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SimObjectParam<AlphaISA::DTB *> dtb;
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Param<Tick> profile;
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@ -161,11 +161,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM_DFLT(phase, "clock phase", 0),
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INIT_PARAM(numThreads, "number of HW thread contexts"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM_DFLT(activity, "Initial activity count", 0),
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#if FULL_SYSTEM
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INIT_PARAM(system, "System object"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(profile, ""),
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@ -305,14 +305,15 @@ CREATE_SIM_OBJECT(DerivO3CPU)
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AlphaSimpleParams *params = new AlphaSimpleParams;
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params->clock = clock;
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params->phase = phase;
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params->name = getInstanceName();
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params->numberOfThreads = actual_num_threads;
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params->cpu_id = cpu_id;
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params->activity = activity;
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#if FULL_SYSTEM
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params->system = system;
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params->cpu_id = cpu_id;
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params->itb = itb;
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params->dtb = dtb;
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params->profile = profile;
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@ -114,6 +114,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
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#endif
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// Give the thread the TC.
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this->thread[i]->tc = tc;
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this->thread[i]->setCpuId(params->cpu_id);
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// Add the TC to the CPU's list of TC's.
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this->threadContexts.push_back(tc);
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@ -247,6 +247,11 @@ class DefaultCommit
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/** Handles squashing due to an TC write. */
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void squashFromTC(unsigned tid);
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#if FULL_SYSTEM
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/** Handles processing an interrupt. */
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void handleInterrupt();
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#endif // FULL_SYSTEM
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/** Commits as many instructions as possible. */
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void commitInsts();
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@ -409,6 +414,16 @@ class DefaultCommit
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/** The sequence number of the youngest valid instruction in the ROB. */
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InstSeqNum youngestSeqNum[Impl::MaxThreads];
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/** Records if there is a trap currently in flight. */
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bool trapInFlight[Impl::MaxThreads];
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/** Records if there were any stores committed this cycle. */
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bool committedStores[Impl::MaxThreads];
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/** Records if commit should check if the ROB is truly empty (see
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commit_impl.hh). */
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bool checkEmptyROB[Impl::MaxThreads];
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/** Pointer to the list of active threads. */
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std::list<unsigned> *activeThreads;
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@ -118,6 +118,9 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
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for (int i=0; i < numThreads; i++) {
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commitStatus[i] = Idle;
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changedROBNumEntries[i] = false;
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checkEmptyROB[i] = false;
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trapInFlight[i] = false;
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committedStores[i] = false;
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trapSquash[i] = false;
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tcSquash[i] = false;
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PC[i] = nextPC[i] = nextNPC[i] = 0;
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@ -335,6 +338,7 @@ DefaultCommit<Impl>::initStage()
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for (int i=0; i < numThreads; i++) {
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toIEW->commitInfo[i].usedROB = true;
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toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
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toIEW->commitInfo[i].emptyROB = true;
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}
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cpu->activityThisCycle();
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@ -473,14 +477,14 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
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TrapEvent *trap = new TrapEvent(this, tid);
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trap->schedule(curTick + trapLatency);
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thread[tid]->trapPending = true;
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trapInFlight[tid] = true;
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}
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template <class Impl>
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void
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DefaultCommit<Impl>::generateTCEvent(unsigned tid)
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{
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assert(!trapInFlight[tid]);
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DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
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tcSquash[tid] = true;
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@ -495,7 +499,7 @@ DefaultCommit<Impl>::squashAll(unsigned tid)
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// Hopefully this doesn't mess things up. Basically I want to squash
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// all instructions of this thread.
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InstSeqNum squashed_inst = rob->isEmpty() ?
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0 : rob->readHeadInst(tid)->seqNum - 1;;
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0 : rob->readHeadInst(tid)->seqNum - 1;
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// All younger instructions will be squashed. Set the sequence
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// number as the youngest instruction in the ROB (0 in this case.
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@ -532,6 +536,7 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
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thread[tid]->trapPending = false;
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thread[tid]->inSyscall = false;
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trapInFlight[tid] = false;
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trapSquash[tid] = false;
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|
@ -580,6 +585,10 @@ DefaultCommit<Impl>::tick()
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while (threads != end) {
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unsigned tid = *threads++;
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// Clear the bit saying if the thread has committed stores
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// this cycle.
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committedStores[tid] = false;
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if (commitStatus[tid] == ROBSquashing) {
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if (rob->isDoneSquashing(tid)) {
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|
@ -635,16 +644,11 @@ DefaultCommit<Impl>::tick()
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updateStatus();
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}
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#if FULL_SYSTEM
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template <class Impl>
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void
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DefaultCommit<Impl>::commit()
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DefaultCommit<Impl>::handleInterrupt()
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{
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//////////////////////////////////////
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// Check for interrupts
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//////////////////////////////////////
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#if FULL_SYSTEM
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if (interrupt != NoFault) {
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// Wait until the ROB is empty and all stores have drained in
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// order to enter the interrupt.
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|
@ -653,6 +657,12 @@ DefaultCommit<Impl>::commit()
|
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// an interrupt needed to be handled.
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DPRINTF(Commit, "Interrupt detected.\n");
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|
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Fault new_interrupt = cpu->getInterrupts();
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assert(new_interrupt == interrupt);
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// Clear the interrupt now that it's going to be handled
|
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toIEW->commitInfo[0].clearInterrupt = true;
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assert(!thread[0]->inSyscall);
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thread[0]->inSyscall = true;
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|
@ -666,14 +676,12 @@ DefaultCommit<Impl>::commit()
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// Generate trap squash event.
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generateTrapEvent(0);
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// Clear the interrupt now that it's been handled
|
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toIEW->commitInfo[0].clearInterrupt = true;
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interrupt = NoFault;
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} else {
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DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
|
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}
|
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} else if (cpu->check_interrupts(cpu->tcBase(0)) &&
|
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commitStatus[0] != TrapPending &&
|
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} else if (commitStatus[0] != TrapPending &&
|
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cpu->check_interrupts(cpu->tcBase(0)) &&
|
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!trapSquash[0] &&
|
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!tcSquash[0]) {
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// Process interrupts if interrupts are enabled, not in PAL
|
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|
@ -691,7 +699,21 @@ DefaultCommit<Impl>::commit()
|
|||
toIEW->commitInfo[0].interruptPending = true;
|
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}
|
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}
|
||||
}
|
||||
#endif // FULL_SYSTEM
|
||||
|
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template <class Impl>
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void
|
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DefaultCommit<Impl>::commit()
|
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{
|
||||
|
||||
#if FULL_SYSTEM
|
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// Check for any interrupt, and start processing it. Or if we
|
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// have an outstanding interrupt and are at a point when it is
|
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// valid to take an interrupt, process it.
|
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if (cpu->check_interrupts(cpu->tcBase(0))) {
|
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handleInterrupt();
|
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}
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
////////////////////////////////////
|
||||
|
@ -709,6 +731,7 @@ DefaultCommit<Impl>::commit()
|
|||
assert(!tcSquash[tid]);
|
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squashFromTrap(tid);
|
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} else if (tcSquash[tid] == true) {
|
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assert(commitStatus[tid] != TrapPending);
|
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squashFromTC(tid);
|
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}
|
||||
|
||||
|
@ -753,6 +776,7 @@ DefaultCommit<Impl>::commit()
|
|||
bdelay_done_seq_num--;
|
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#endif
|
||||
}
|
||||
|
||||
// All younger instructions will be squashed. Set the sequence
|
||||
// number as the youngest instruction in the ROB.
|
||||
youngestSeqNum[tid] = squashed_inst;
|
||||
|
@ -817,13 +841,29 @@ DefaultCommit<Impl>::commit()
|
|||
toIEW->commitInfo[tid].usedROB = true;
|
||||
toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
|
||||
|
||||
if (rob->isEmpty(tid)) {
|
||||
toIEW->commitInfo[tid].emptyROB = true;
|
||||
}
|
||||
|
||||
wroteToTimeBuffer = true;
|
||||
changedROBNumEntries[tid] = false;
|
||||
if (rob->isEmpty(tid))
|
||||
checkEmptyROB[tid] = true;
|
||||
}
|
||||
|
||||
// ROB is only considered "empty" for previous stages if: a)
|
||||
// ROB is empty, b) there are no outstanding stores, c) IEW
|
||||
// stage has received any information regarding stores that
|
||||
// committed.
|
||||
// c) is checked by making sure to not consider the ROB empty
|
||||
// on the same cycle as when stores have been committed.
|
||||
// @todo: Make this handle multi-cycle communication between
|
||||
// commit and IEW.
|
||||
if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
|
||||
!iewStage->hasStoresToWB() && !committedStores[tid]) {
|
||||
checkEmptyROB[tid] = false;
|
||||
toIEW->commitInfo[tid].usedROB = true;
|
||||
toIEW->commitInfo[tid].emptyROB = true;
|
||||
toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
|
||||
wroteToTimeBuffer = true;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -966,8 +1006,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
// and committed this instruction.
|
||||
thread[tid]->funcExeInst--;
|
||||
|
||||
head_inst->setAtCommit();
|
||||
|
||||
if (head_inst->isNonSpeculative() ||
|
||||
head_inst->isStoreConditional() ||
|
||||
head_inst->isMemBarrier() ||
|
||||
|
@ -977,19 +1015,9 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
"instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
|
||||
head_inst->seqNum, head_inst->readPC());
|
||||
|
||||
// Hack to make sure syscalls/memory barriers/quiesces
|
||||
// aren't executed until all stores write back their data.
|
||||
// This direct communication shouldn't be used for
|
||||
// anything other than this.
|
||||
if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
|
||||
head_inst->isQuiesce()) &&
|
||||
iewStage->hasStoresToWB())
|
||||
{
|
||||
if (inst_num > 0 || iewStage->hasStoresToWB()) {
|
||||
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
|
||||
return false;
|
||||
} else if (inst_num > 0 || iewStage->hasStoresToWB()) {
|
||||
DPRINTF(Commit, "Waiting to become head of commit.\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
|
||||
|
@ -1002,6 +1030,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
|
||||
return false;
|
||||
} else if (head_inst->isLoad()) {
|
||||
if (inst_num > 0 || iewStage->hasStoresToWB()) {
|
||||
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
assert(head_inst->uncacheable());
|
||||
DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
|
||||
head_inst->seqNum, head_inst->readPC());
|
||||
|
||||
|
@ -1025,8 +1059,11 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
panic("Thread sync instructions are not handled yet.\n");
|
||||
}
|
||||
|
||||
// Check if the instruction caused a fault. If so, trap.
|
||||
Fault inst_fault = head_inst->getFault();
|
||||
|
||||
// Stores mark themselves as completed.
|
||||
if (!head_inst->isStore()) {
|
||||
if (!head_inst->isStore() && inst_fault == NoFault) {
|
||||
head_inst->setCompleted();
|
||||
}
|
||||
|
||||
|
@ -1038,9 +1075,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
}
|
||||
#endif
|
||||
|
||||
// Check if the instruction caused a fault. If so, trap.
|
||||
Fault inst_fault = head_inst->getFault();
|
||||
|
||||
// DTB will sometimes need the machine instruction for when
|
||||
// faults happen. So we will set it here, prior to the DTB
|
||||
// possibly needing it for its fault.
|
||||
|
@ -1048,7 +1082,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
|
||||
|
||||
if (inst_fault != NoFault) {
|
||||
head_inst->setCompleted();
|
||||
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
|
||||
head_inst->seqNum, head_inst->readPC());
|
||||
|
||||
|
@ -1057,6 +1090,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
return false;
|
||||
}
|
||||
|
||||
head_inst->setCompleted();
|
||||
|
||||
#if USE_CHECKER
|
||||
if (cpu->checker && head_inst->isStore()) {
|
||||
cpu->checker->verify(head_inst);
|
||||
|
@ -1082,6 +1117,13 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
|
||||
commitStatus[tid] = TrapPending;
|
||||
|
||||
if (head_inst->traceData) {
|
||||
head_inst->traceData->setFetchSeq(head_inst->seqNum);
|
||||
head_inst->traceData->setCPSeq(thread[tid]->numInst);
|
||||
head_inst->traceData->finalize();
|
||||
head_inst->traceData = NULL;
|
||||
}
|
||||
|
||||
// Generate trap squash event.
|
||||
generateTrapEvent(tid);
|
||||
// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
|
||||
|
@ -1123,6 +1165,10 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
|
|||
// Finally clear the head ROB entry.
|
||||
rob->retireHead(tid);
|
||||
|
||||
// If this was a store, record it for this cycle.
|
||||
if (head_inst->isStore())
|
||||
committedStores[tid] = true;
|
||||
|
||||
// Return true to indicate that we have committed an instruction.
|
||||
return true;
|
||||
}
|
||||
|
@ -1167,7 +1213,8 @@ DefaultCommit<Impl>::getInsts()
|
|||
int tid = inst->threadNumber;
|
||||
|
||||
if (!inst->isSquashed() &&
|
||||
commitStatus[tid] != ROBSquashing) {
|
||||
commitStatus[tid] != ROBSquashing &&
|
||||
commitStatus[tid] != TrapPending) {
|
||||
changedROBNumEntries[tid] = true;
|
||||
|
||||
DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
|
||||
|
|
|
@ -466,7 +466,7 @@ FullO3CPU<Impl>::tick()
|
|||
lastRunningCycle = curTick;
|
||||
timesIdled++;
|
||||
} else {
|
||||
tickEvent.schedule(curTick + cycles(1));
|
||||
tickEvent.schedule(nextCycle(curTick + cycles(1)));
|
||||
DPRINTF(O3CPU, "Scheduling next tick!\n");
|
||||
}
|
||||
}
|
||||
|
@ -886,7 +886,7 @@ FullO3CPU<Impl>::resume()
|
|||
#endif
|
||||
|
||||
if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick);
|
||||
tickEvent.schedule(nextCycle());
|
||||
_status = Running;
|
||||
}
|
||||
|
||||
|
@ -979,11 +979,11 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
|
|||
ThreadContext *tc = threadContexts[i];
|
||||
if (tc->status() == ThreadContext::Active && _status != Running) {
|
||||
_status = Running;
|
||||
tickEvent.schedule(curTick);
|
||||
tickEvent.schedule(nextCycle());
|
||||
}
|
||||
}
|
||||
if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick);
|
||||
tickEvent.schedule(nextCycle());
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -1393,7 +1393,7 @@ FullO3CPU<Impl>::wakeCPU()
|
|||
|
||||
idleCycles += (curTick - 1) - lastRunningCycle;
|
||||
|
||||
tickEvent.schedule(curTick);
|
||||
tickEvent.schedule(nextCycle());
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
|
|
@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
|
|||
void scheduleTickEvent(int delay)
|
||||
{
|
||||
if (tickEvent.squashed())
|
||||
tickEvent.reschedule(curTick + cycles(delay));
|
||||
tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
|
||||
else if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick + cycles(delay));
|
||||
tickEvent.schedule(nextCycle(curTick + cycles(delay)));
|
||||
}
|
||||
|
||||
/** Unschedule tick event, regardless of its current state. */
|
||||
|
@ -186,9 +186,11 @@ class FullO3CPU : public BaseO3CPU
|
|||
{
|
||||
// Schedule thread to activate, regardless of its current state.
|
||||
if (activateThreadEvent[tid].squashed())
|
||||
activateThreadEvent[tid].reschedule(curTick + cycles(delay));
|
||||
activateThreadEvent[tid].
|
||||
reschedule(nextCycle(curTick + cycles(delay)));
|
||||
else if (!activateThreadEvent[tid].scheduled())
|
||||
activateThreadEvent[tid].schedule(curTick + cycles(delay));
|
||||
activateThreadEvent[tid].
|
||||
schedule(nextCycle(curTick + cycles(delay)));
|
||||
}
|
||||
|
||||
/** Unschedule actiavte thread event, regardless of its current state. */
|
||||
|
@ -235,9 +237,11 @@ class FullO3CPU : public BaseO3CPU
|
|||
{
|
||||
// Schedule thread to activate, regardless of its current state.
|
||||
if (deallocateContextEvent[tid].squashed())
|
||||
deallocateContextEvent[tid].reschedule(curTick + cycles(delay));
|
||||
deallocateContextEvent[tid].
|
||||
reschedule(nextCycle(curTick + cycles(delay)));
|
||||
else if (!deallocateContextEvent[tid].scheduled())
|
||||
deallocateContextEvent[tid].schedule(curTick + cycles(delay));
|
||||
deallocateContextEvent[tid].
|
||||
schedule(nextCycle(curTick + cycles(delay)));
|
||||
}
|
||||
|
||||
/** Unschedule thread deallocation in CPU */
|
||||
|
|
|
@ -620,6 +620,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
|
|||
fault = TheISA::genMachineCheckFault();
|
||||
delete mem_req;
|
||||
memReq[tid] = NULL;
|
||||
warn("Bad address!\n");
|
||||
}
|
||||
assert(retryPkt == NULL);
|
||||
assert(retryTid == -1);
|
||||
|
@ -670,11 +671,12 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC,
|
|||
// Get rid of the retrying packet if it was from this thread.
|
||||
if (retryTid == tid) {
|
||||
assert(cacheBlocked);
|
||||
cacheBlocked = false;
|
||||
retryTid = -1;
|
||||
if (retryPkt) {
|
||||
delete retryPkt->req;
|
||||
delete retryPkt;
|
||||
}
|
||||
retryPkt = NULL;
|
||||
retryTid = -1;
|
||||
}
|
||||
|
||||
fetchStatus[tid] = Squashing;
|
||||
|
@ -1150,7 +1152,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
|||
|
||||
///FIXME This needs to be more robust in dealing with delay slots
|
||||
#if !ISA_HAS_DELAY_SLOT
|
||||
predicted_branch |=
|
||||
// predicted_branch |=
|
||||
#endif
|
||||
lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
|
||||
predicted_branch |= (next_PC != fetch_NPC);
|
||||
|
@ -1221,7 +1223,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
|||
// until commit handles the fault. The only other way it can
|
||||
// wake up is if a squash comes along and changes the PC.
|
||||
#if FULL_SYSTEM
|
||||
assert(numInst != fetchWidth);
|
||||
assert(numInst < fetchWidth);
|
||||
// Get a sequence number.
|
||||
inst_seq = cpu->getAndIncrementInstSeq();
|
||||
// We will use a nop in order to carry the fault.
|
||||
|
|
|
@ -1152,19 +1152,6 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
|
|||
// Same as non-speculative stores.
|
||||
inst->setCanCommit();
|
||||
instQueue.insertBarrier(inst);
|
||||
add_to_iq = false;
|
||||
} else if (inst->isNonSpeculative()) {
|
||||
DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
|
||||
"encountered, skipping.\n", tid);
|
||||
|
||||
// Same as non-speculative stores.
|
||||
inst->setCanCommit();
|
||||
|
||||
// Specifically insert it as nonspeculative.
|
||||
instQueue.insertNonSpec(inst);
|
||||
|
||||
++iewDispNonSpecInsts;
|
||||
|
||||
add_to_iq = false;
|
||||
} else if (inst->isNop()) {
|
||||
DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
|
||||
|
@ -1193,6 +1180,20 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
|
|||
} else {
|
||||
add_to_iq = true;
|
||||
}
|
||||
if (inst->isNonSpeculative()) {
|
||||
DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
|
||||
"encountered, skipping.\n", tid);
|
||||
|
||||
// Same as non-speculative stores.
|
||||
inst->setCanCommit();
|
||||
|
||||
// Specifically insert it as nonspeculative.
|
||||
instQueue.insertNonSpec(inst);
|
||||
|
||||
++iewDispNonSpecInsts;
|
||||
|
||||
add_to_iq = false;
|
||||
}
|
||||
|
||||
// If the instruction queue is not full, then add the
|
||||
// instruction.
|
||||
|
@ -1379,6 +1380,7 @@ DefaultIEW<Impl>::executeInsts()
|
|||
predictedNotTakenIncorrect++;
|
||||
}
|
||||
} else if (ldstQueue.violation(tid)) {
|
||||
assert(inst->isMemRef());
|
||||
// If there was an ordering violation, then get the
|
||||
// DynInst that caused the violation. Note that this
|
||||
// clears the violation signal.
|
||||
|
@ -1391,10 +1393,10 @@ DefaultIEW<Impl>::executeInsts()
|
|||
|
||||
// Ensure the violating instruction is older than
|
||||
// current squash
|
||||
if (fetchRedirect[tid] &&
|
||||
violator->seqNum >= toCommit->squashedSeqNum[tid])
|
||||
/* if (fetchRedirect[tid] &&
|
||||
violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
|
||||
continue;
|
||||
|
||||
*/
|
||||
fetchRedirect[tid] = true;
|
||||
|
||||
// Tell the instruction queue that a violation has occured.
|
||||
|
@ -1414,6 +1416,33 @@ DefaultIEW<Impl>::executeInsts()
|
|||
|
||||
squashDueToMemBlocked(inst, tid);
|
||||
}
|
||||
} else {
|
||||
// Reset any state associated with redirects that will not
|
||||
// be used.
|
||||
if (ldstQueue.violation(tid)) {
|
||||
assert(inst->isMemRef());
|
||||
|
||||
DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
|
||||
|
||||
DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
|
||||
"%#x, inst PC: %#x. Addr is: %#x.\n",
|
||||
violator->readPC(), inst->readPC(), inst->physEffAddr);
|
||||
DPRINTF(IEW, "Violation will not be handled because "
|
||||
"already squashing\n");
|
||||
|
||||
++memOrderViolationEvents;
|
||||
}
|
||||
if (ldstQueue.loadBlocked(tid) &&
|
||||
!ldstQueue.isLoadBlockedHandled(tid)) {
|
||||
DPRINTF(IEW, "Load operation couldn't execute because the "
|
||||
"memory system is blocked. PC: %#x [sn:%lli]\n",
|
||||
inst->readPC(), inst->seqNum);
|
||||
DPRINTF(IEW, "Blocked load will not be handled because "
|
||||
"already squashing\n");
|
||||
|
||||
ldstQueue.setLoadBlockedHandled(tid);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1563,6 +1592,7 @@ DefaultIEW<Impl>::tick()
|
|||
//DPRINTF(IEW,"NonspecInst from thread %i",tid);
|
||||
if (fromCommit->commitInfo[tid].uncached) {
|
||||
instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
|
||||
fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
|
||||
} else {
|
||||
instQueue.scheduleNonSpec(
|
||||
fromCommit->commitInfo[tid].nonSpecSeqNum);
|
||||
|
|
|
@ -829,6 +829,8 @@ InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
|
|||
|
||||
unsigned tid = (*inst_it).second->threadNumber;
|
||||
|
||||
(*inst_it).second->setAtCommit();
|
||||
|
||||
(*inst_it).second->setCanIssue();
|
||||
|
||||
if (!(*inst_it).second->isMemRef()) {
|
||||
|
@ -960,6 +962,8 @@ template <class Impl>
|
|||
void
|
||||
InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
|
||||
{
|
||||
DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
|
||||
resched_inst->clearCanIssue();
|
||||
memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
|
||||
}
|
||||
|
||||
|
@ -984,7 +988,6 @@ InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
|
|||
completed_inst->memOpDone = true;
|
||||
|
||||
memDepUnit[tid].completed(completed_inst);
|
||||
|
||||
count[tid]--;
|
||||
}
|
||||
|
||||
|
@ -1084,10 +1087,14 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
|
|||
|
||||
++iqSquashedOperandsExamined;
|
||||
}
|
||||
} else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) {
|
||||
} else if (!squashed_inst->isStoreConditional() ||
|
||||
!squashed_inst->isCompleted()) {
|
||||
NonSpecMapIt ns_inst_it =
|
||||
nonSpecInsts.find(squashed_inst->seqNum);
|
||||
assert(ns_inst_it != nonSpecInsts.end());
|
||||
if (ns_inst_it == nonSpecInsts.end()) {
|
||||
assert(squashed_inst->getFault() != NoFault);
|
||||
} else {
|
||||
|
||||
(*ns_inst_it).second = NULL;
|
||||
|
||||
|
@ -1095,6 +1102,7 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
|
|||
|
||||
++iqSquashedNonSpecRemoved;
|
||||
}
|
||||
}
|
||||
|
||||
// Might want to also clear out the head of the dependency graph.
|
||||
|
||||
|
|
|
@ -497,6 +497,11 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
(load_idx != loadHead || !load_inst->isAtCommit())) {
|
||||
iewStage->rescheduleMemInst(load_inst);
|
||||
++lsqRescheduledLoads;
|
||||
|
||||
// Must delete request now that it wasn't handed off to
|
||||
// memory. This is quite ugly. @todo: Figure out the proper
|
||||
// place to really handle request deletes.
|
||||
delete req;
|
||||
return TheISA::genMachineCheckFault();
|
||||
}
|
||||
|
||||
|
@ -534,6 +539,10 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
|
||||
if (store_size == 0)
|
||||
continue;
|
||||
else if (storeQueue[store_idx].inst->uncacheable())
|
||||
continue;
|
||||
|
||||
assert(storeQueue[store_idx].inst->effAddrValid);
|
||||
|
||||
// Check if the store data is within the lower and upper bounds of
|
||||
// addresses that the request needs.
|
||||
|
@ -550,7 +559,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
storeQueue[store_idx].inst->effAddr;
|
||||
|
||||
// If the store's data has all of the data needed, we can forward.
|
||||
if (store_has_lower_limit && store_has_upper_limit) {
|
||||
if ((store_has_lower_limit && store_has_upper_limit)) {
|
||||
// Get shift amount for offset into the store's data.
|
||||
int shift_amt = req->getVaddr() & (store_size - 1);
|
||||
// @todo: Magic number, assumes byte addressing
|
||||
|
@ -596,6 +605,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
// If it's already been written back, then don't worry about
|
||||
// stalling on it.
|
||||
if (storeQueue[store_idx].completed) {
|
||||
panic("Should not check one of these");
|
||||
continue;
|
||||
}
|
||||
|
||||
|
@ -614,6 +624,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
// rescheduled eventually
|
||||
iewStage->rescheduleMemInst(load_inst);
|
||||
iewStage->decrWb(load_inst->seqNum);
|
||||
load_inst->clearIssued();
|
||||
++lsqRescheduledLoads;
|
||||
|
||||
// Do not generate a writeback event as this instruction is not
|
||||
|
@ -622,7 +633,11 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
"Store idx %i to load addr %#x\n",
|
||||
store_idx, req->getVaddr());
|
||||
|
||||
++lsqBlockedLoads;
|
||||
// Must delete request now that it wasn't handed off to
|
||||
// memory. This is quite ugly. @todo: Figure out the
|
||||
// proper place to really handle request deletes.
|
||||
delete req;
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
}
|
||||
|
@ -654,8 +669,11 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
// Delete state and data packet because a load retry
|
||||
// initiates a pipeline restart; it does not retry.
|
||||
delete state;
|
||||
delete data_pkt->req;
|
||||
delete data_pkt;
|
||||
|
||||
req = NULL;
|
||||
|
||||
if (result == Packet::BadAddress) {
|
||||
return TheISA::genMachineCheckFault();
|
||||
}
|
||||
|
@ -669,6 +687,9 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
|||
// If the cache was blocked, or has become blocked due to the access,
|
||||
// handle it.
|
||||
if (lsq->cacheBlocked()) {
|
||||
if (req)
|
||||
delete req;
|
||||
|
||||
++lsqCacheBlocked;
|
||||
|
||||
iewStage->decrWb(load_inst->seqNum);
|
||||
|
|
|
@ -81,6 +81,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
|
|||
if (isSwitchedOut() || inst->isSquashed()) {
|
||||
iewStage->decrWb(inst->seqNum);
|
||||
delete state;
|
||||
delete pkt->req;
|
||||
delete pkt;
|
||||
return;
|
||||
} else {
|
||||
|
@ -94,6 +95,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
|
|||
}
|
||||
|
||||
delete state;
|
||||
delete pkt->req;
|
||||
delete pkt;
|
||||
}
|
||||
|
||||
|
@ -403,12 +405,15 @@ template <class Impl>
|
|||
Fault
|
||||
LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
||||
{
|
||||
using namespace TheISA;
|
||||
// Execute a specific load.
|
||||
Fault load_fault = NoFault;
|
||||
|
||||
DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
|
||||
inst->readPC(),inst->seqNum);
|
||||
|
||||
assert(!inst->isSquashed());
|
||||
|
||||
load_fault = inst->initiateAcc();
|
||||
|
||||
// If the instruction faulted, then we need to send it along to commit
|
||||
|
@ -418,12 +423,44 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
|||
// realizes there is activity.
|
||||
// Mark it as executed unless it is an uncached load that
|
||||
// needs to hit the head of commit.
|
||||
if (!(inst->req && inst->req->isUncacheable()) ||
|
||||
if (!(inst->hasRequest() && inst->uncacheable()) ||
|
||||
inst->isAtCommit()) {
|
||||
inst->setExecuted();
|
||||
}
|
||||
iewStage->instToCommit(inst);
|
||||
iewStage->activityThisCycle();
|
||||
} else if (!loadBlocked()) {
|
||||
assert(inst->effAddrValid);
|
||||
int load_idx = inst->lqIdx;
|
||||
incrLdIdx(load_idx);
|
||||
while (load_idx != loadTail) {
|
||||
// Really only need to check loads that have actually executed
|
||||
|
||||
// @todo: For now this is extra conservative, detecting a
|
||||
// violation if the addresses match assuming all accesses
|
||||
// are quad word accesses.
|
||||
|
||||
// @todo: Fix this, magic number being used here
|
||||
if (loadQueue[load_idx]->effAddrValid &&
|
||||
(loadQueue[load_idx]->effAddr >> 8) ==
|
||||
(inst->effAddr >> 8)) {
|
||||
// A load incorrectly passed this load. Squash and refetch.
|
||||
// For now return a fault to show that it was unsuccessful.
|
||||
DynInstPtr violator = loadQueue[load_idx];
|
||||
if (!memDepViolator ||
|
||||
(violator->seqNum < memDepViolator->seqNum)) {
|
||||
memDepViolator = violator;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
|
||||
++lsqMemOrderViolation;
|
||||
|
||||
return genMachineCheckFault();
|
||||
}
|
||||
|
||||
incrLdIdx(load_idx);
|
||||
}
|
||||
}
|
||||
|
||||
return load_fault;
|
||||
|
@ -442,6 +479,8 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|||
DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
|
||||
store_inst->readPC(), store_inst->seqNum);
|
||||
|
||||
assert(!store_inst->isSquashed());
|
||||
|
||||
// Check the recently completed loads to see if any match this store's
|
||||
// address. If so, then we have a memory ordering violation.
|
||||
int load_idx = store_inst->lqIdx;
|
||||
|
@ -465,7 +504,7 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|||
++storesToWB;
|
||||
}
|
||||
|
||||
if (!memDepViolator) {
|
||||
assert(store_inst->effAddrValid);
|
||||
while (load_idx != loadTail) {
|
||||
// Really only need to check loads that have actually executed
|
||||
// It's safe to check all loads because effAddr is set to
|
||||
|
@ -476,11 +515,19 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|||
// are quad word accesses.
|
||||
|
||||
// @todo: Fix this, magic number being used here
|
||||
if ((loadQueue[load_idx]->effAddr >> 8) ==
|
||||
if (loadQueue[load_idx]->effAddrValid &&
|
||||
(loadQueue[load_idx]->effAddr >> 8) ==
|
||||
(store_inst->effAddr >> 8)) {
|
||||
// A load incorrectly passed this store. Squash and refetch.
|
||||
// For now return a fault to show that it was unsuccessful.
|
||||
memDepViolator = loadQueue[load_idx];
|
||||
DynInstPtr violator = loadQueue[load_idx];
|
||||
if (!memDepViolator ||
|
||||
(violator->seqNum < memDepViolator->seqNum)) {
|
||||
memDepViolator = violator;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
|
||||
++lsqMemOrderViolation;
|
||||
|
||||
return genMachineCheckFault();
|
||||
|
@ -489,10 +536,6 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|||
incrLdIdx(load_idx);
|
||||
}
|
||||
|
||||
// If we've reached this point, there was no violation.
|
||||
memDepViolator = NULL;
|
||||
}
|
||||
|
||||
return store_fault;
|
||||
}
|
||||
|
||||
|
@ -660,7 +703,7 @@ LSQUnit<Impl>::writebackStores()
|
|||
panic("LSQ sent out a bad address for a completed store!");
|
||||
}
|
||||
// Need to handle becoming blocked on a store.
|
||||
DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
|
||||
DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
|
||||
"retry later\n",
|
||||
inst->seqNum);
|
||||
isStoreBlocked = true;
|
||||
|
@ -735,6 +778,10 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|||
}
|
||||
}
|
||||
|
||||
if (memDepViolator && squashed_num < memDepViolator->seqNum) {
|
||||
memDepViolator = NULL;
|
||||
}
|
||||
|
||||
int store_idx = storeTail;
|
||||
decrStIdx(store_idx);
|
||||
|
||||
|
@ -764,6 +811,11 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|||
storeQueue[store_idx].inst = NULL;
|
||||
storeQueue[store_idx].canWB = 0;
|
||||
|
||||
// Must delete request now that it wasn't handed off to
|
||||
// memory. This is quite ugly. @todo: Figure out the proper
|
||||
// place to really handle request deletes.
|
||||
delete storeQueue[store_idx].req;
|
||||
|
||||
storeQueue[store_idx].req = NULL;
|
||||
--stores;
|
||||
|
||||
|
|
|
@ -214,6 +214,9 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
|
|||
inst_entry->regsReady = true;
|
||||
}
|
||||
|
||||
// Clear the bit saying this instruction can issue.
|
||||
inst->clearCanIssue();
|
||||
|
||||
// Add this instruction to the list of dependents.
|
||||
store_entry->dependInsts.push_back(inst_entry);
|
||||
|
||||
|
@ -357,7 +360,6 @@ void
|
|||
MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
|
||||
{
|
||||
DynInstPtr temp_inst;
|
||||
bool found_inst = false;
|
||||
|
||||
// For now this replay function replays all waiting memory ops.
|
||||
while (!instsToReplay.empty()) {
|
||||
|
@ -371,14 +373,8 @@ MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
|
|||
|
||||
moveToReady(inst_entry);
|
||||
|
||||
if (temp_inst == inst) {
|
||||
found_inst = true;
|
||||
}
|
||||
|
||||
instsToReplay.pop_front();
|
||||
}
|
||||
|
||||
assert(found_inst);
|
||||
}
|
||||
|
||||
template <class MemDepPred, class Impl>
|
||||
|
|
|
@ -192,8 +192,6 @@ SimpleRenameMap::rename(RegIndex arch_reg)
|
|||
// known that the prev reg was outside the range of normal registers
|
||||
// so the free list can avoid adding it.
|
||||
prev_reg = renamed_reg;
|
||||
|
||||
assert(renamed_reg < numPhysicalRegs + numMiscRegs);
|
||||
}
|
||||
|
||||
DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
|
||||
|
|
|
@ -171,8 +171,12 @@ Bus::recvTiming(PacketPtr pkt)
|
|||
}
|
||||
|
||||
short dest = pkt->getDest();
|
||||
|
||||
// Make sure to clear the snoop commit flag so it doesn't think an
|
||||
// access has been handled twice.
|
||||
if (dest == Packet::Broadcast) {
|
||||
port = findPort(pkt->getAddr(), pkt->getSrc());
|
||||
pkt->flags &= ~SNOOP_COMMIT;
|
||||
if (timingSnoop(pkt, port ? port : interfaces[pkt->getSrc()])) {
|
||||
bool success;
|
||||
|
||||
|
|
5
src/mem/cache/cache_impl.hh
vendored
5
src/mem/cache/cache_impl.hh
vendored
|
@ -545,8 +545,13 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
|
|||
//We are determining prefetches on access stream, call prefetcher
|
||||
prefetcher->handleMiss(pkt, curTick);
|
||||
}
|
||||
|
||||
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
|
||||
|
||||
if (!pkt->req->isUncacheable()) {
|
||||
if (!missQueue->findMSHR(blk_addr)) {
|
||||
blk = handleAccess(pkt, lat, writebacks);
|
||||
}
|
||||
} else {
|
||||
size = pkt->getSize();
|
||||
}
|
||||
|
|
1
src/mem/cache/miss/miss_queue.cc
vendored
1
src/mem/cache/miss/miss_queue.cc
vendored
|
@ -599,6 +599,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time)
|
|||
MemCmd cmd = mshr->getTarget()->cmd;
|
||||
mshr->pkt->setDest(Packet::Broadcast);
|
||||
mshr->pkt->result = Packet::Unknown;
|
||||
mshr->pkt->req = mshr->getTarget()->req;
|
||||
mq.markPending(mshr, cmd);
|
||||
mshr->order = order++;
|
||||
cache->setMasterRequest(Request_MSHR, time);
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
@ -37,7 +37,7 @@ class MyCache(BaseCache):
|
|||
mshrs = 10
|
||||
tgts_per_mshr = 5
|
||||
|
||||
cpu = DerivO3CPU()
|
||||
cpu = DerivO3CPU(cpu_id=0)
|
||||
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
|
||||
MyCache(size = '2MB'))
|
||||
|
||||
|
|
Loading…
Reference in a new issue