sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

stats: Update x86 stats after x87 fixes

Browse source 
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
This commit is contained in:
Andreas Sandberg 2013-10-02 11:03:38 +02:00
parent d3d53938c0
commit 0438bf9389
25 changed files with 5542 additions and 5532 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
@ -661,8 +661,8 @@ voltage_domain=system.voltage_domain
[system.e820_table]
type=X86E820Table
children=entries0 entries1 entries2
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
[system.e820_table.entries0]
type=X86E820Entry
@ -682,6 +682,12 @@ addr=1048576
range_type=1
size=133169152
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
range_type=2
size=65536
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
@ -1350,7 +1356,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-x86.img
image_file=/scratch/andreas/m5/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1370,7 +1376,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

1
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
View file

@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unimplemented function 8

12
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:54:38
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5133762710000 because m5_exit instruction encountered
Exiting @ tick 5133817564000 because m5_exit instruction encountered

2609
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

11
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
View file

@ -4,8 +4,9 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
end_pfn_map = 32768
kernel direct mapping tables up to 8000000 @ 8000-a000
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@ -22,8 +23,8 @@ Setting APIC routing to flat
Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
Built 1 zonelists. Total pages: 30613
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
Built 1 zonelists. Total pages: 30612
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@ -33,7 +34,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

16
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
mem_ranges=0:134217727
@ -681,8 +681,8 @@ voltage_domain=system.voltage_domain
[system.e820_table]
type=X86E820Table
children=entries0 entries1 entries2
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
[system.e820_table.entries0]
type=X86E820Entry
@ -702,6 +702,12 @@ addr=1048576
range_type=1
size=133169152
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
range_type=2
size=65536
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
@ -1401,7 +1407,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-x86.img
image_file=/scratch/andreas/m5/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1421,7 +1427,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

2
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
View file

@ -4,7 +4,7 @@ warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
hack: be nice to actually delete the event here
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0xbacc
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unimplemented function 8

2904
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
View file

File diff suppressed because it is too large Load diff

13
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
View file

@ -4,8 +4,9 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
end_pfn_map = 32768
kernel direct mapping tables up to 8000000 @ 8000-a000
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@ -22,8 +23,8 @@ Setting APIC routing to flat
Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
Built 1 zonelists. Total pages: 30613
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
Built 1 zonelists. Total pages: 30612
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@ -33,7 +34,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@ -43,7 +44,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
result 7812464
result 7812463
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1

10
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 07:10:19
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -81,4 +79,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 458201684000 because target called exit()
Exiting @ tick 458275427000 because target called exit()

1597
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

10
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:27:45
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
@ -26,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 144470654000 because target called exit()
122 123 124 Exiting @ tick 144337151000 because target called exit()

1358
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

10
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:58:25
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
@ -26,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 131393068000 because target called exit()
122 123 124 Exiting @ tick 131393279000 because target called exit()

44
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393068000 # Number of ticks simulated
final_tick 131393068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1192575 # Simulator instruction rate (inst/s)
host_op_rate 1998860 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1186450761 # Simulator tick rate (ticks/s)
host_mem_usage 265260 # Number of bytes of host memory used
host_seconds 110.74 # Real time elapsed on the host
host_inst_rate 399836 # Simulator instruction rate (inst/s)
host_op_rate 670162 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 397783827 # Simulator tick rate (ticks/s)
host_mem_usage 267400 # Number of bytes of host memory used
host_seconds 330.31 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362963 # Number of ops (including micro ops) simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
@ -23,25 +23,25 @@ system.physmem.num_reads::cpu.data 56682005 # Nu
system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10563380223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362558061 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925938285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563380223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563380223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759721898 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759721898 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 13685660183 # Throughput (bytes/s)
system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 13685638205 # Throughput (bytes/s)
system.membus.data_through_bus 1798200879 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786137 # number of cpu cycles simulated
system.cpu.numCycles 262786559 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
@ -56,7 +56,7 @@ system.cpu.num_mem_refs 77165304 # nu
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 262786137 # Number of busy cycles
system.cpu.num_busy_cycles 262786559 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

8
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:21:36
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:49:39
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2

14
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 0.250954 # Nu
sim_ticks 250953957000 # Number of ticks simulated
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 352771 # Simulator instruction rate (inst/s)
host_op_rate 591275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 670313887 # Simulator tick rate (ticks/s)
host_mem_usage 270496 # Number of bytes of host memory used
host_seconds 374.38 # Real time elapsed on the host
host_inst_rate 290889 # Simulator instruction rate (inst/s)
host_op_rate 487557 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 552730735 # Simulator tick rate (ticks/s)
host_mem_usage 274892 # Number of bytes of host memory used
host_seconds 454.03 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362963 # Number of ops (including micro ops) simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
@ -49,7 +49,7 @@ system.cpu.numCycles 501907914 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured

16
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
mem_ranges=0:134217727
@ -334,8 +334,8 @@ voltage_domain=system.voltage_domain
[system.e820_table]
type=X86E820Table
children=entries0 entries1 entries2
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
[system.e820_table.entries0]
type=X86E820Entry
@ -355,6 +355,12 @@ addr=1048576
range_type=1
size=133169152
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
range_type=2
size=65536
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
@ -1023,7 +1029,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-x86.img
image_file=/scratch/andreas/m5/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1043,7 +1049,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

1
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
View file

@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: Tried to clear PCI interrupt 14
warn: Unknown mouse command 0xe1.

12
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 07:08:04
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:03:55
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112102211000 because m5_exit instruction encountered
Exiting @ tick 5112126311000 because m5_exit instruction encountered

456
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View file

@ -1,51 +1,51 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.112102 # Number of seconds simulated
sim_ticks 5112102211000 # Number of ticks simulated
final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 5.112126 # Number of seconds simulated
sim_ticks 5112126311000 # Number of ticks simulated
final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 856407 # Simulator instruction rate (inst/s)
host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
host_mem_usage 584104 # Number of bytes of host memory used
host_seconds 233.43 # Real time elapsed on the host
sim_insts 199908396 # Number of instructions simulated
sim_ops 409304707 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
host_inst_rate 1020096 # Simulator instruction rate (inst/s)
host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
host_mem_usage 587152 # Number of bytes of host memory used
host_seconds 195.99 # Real time elapsed on the host
sim_insts 199929810 # Number of instructions simulated
sim_ops 409343980 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory
system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory
system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory
system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory
system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
@ -193,16 +193,16 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.membus.throughput 9632725 # Throughput (bytes/s)
system.membus.data_through_bus 49243475 # Total data (bytes)
system.membus.throughput 9634332 # Throughput (bytes/s)
system.membus.data_through_bus 49251923 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.tags.replacements 47569 # number of replacements
system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
@ -252,59 +252,59 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 2555194 # Throughput (bytes/s)
system.iobus.data_through_bus 13062414 # Total data (bytes)
system.cpu.numCycles 10224204444 # number of cpu cycles simulated
system.iobus.throughput 2555207 # Throughput (bytes/s)
system.iobus.data_through_bus 13062542 # Total data (bytes)
system.cpu.numCycles 10224252644 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199908396 # Number of instructions committed
system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses
system.cpu.committedInsts 199929810 # Number of instructions committed
system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2307395 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls
system.cpu.num_int_insts 374467605 # number of integer instructions
system.cpu.num_func_calls 2307717 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
system.cpu.num_int_insts 374506599 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read
system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written
system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35655576 # number of memory refs
system.cpu.num_load_insts 27235236 # Number of load instructions
system.cpu.num_store_insts 8420340 # Number of store instructions
system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles
system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles
system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
system.cpu.num_mem_refs 35660913 # number of memory refs
system.cpu.num_load_insts 27238816 # Number of load instructions
system.cpu.num_store_insts 8422097 # Number of store instructions
system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles
system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 790522 # number of replacements
system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits
system.cpu.icache.overall_hits::total 243495984 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses
system.cpu.icache.overall_misses::total 791041 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses
system.cpu.icache.tags.replacements 790541 # number of replacements
system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits
system.cpu.icache.overall_hits::total 243525798 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses
system.cpu.icache.overall_misses::total 791060 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
@ -321,14 +321,14 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
@ -369,38 +369,38 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -409,50 +409,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1622027 # number of replacements
system.cpu.dcache.tags.replacements 1622093 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits
system.cpu.dcache.overall_hits::total 20167772 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses
system.cpu.dcache.overall_misses::total 1624823 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits
system.cpu.dcache.overall_hits::total 20172913 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses
system.cpu.dcache.overall_misses::total 1624891 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -461,109 +461,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks
system.cpu.dcache.writebacks::total 1535756 # number of writebacks
system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks
system.cpu.dcache.writebacks::total 1535822 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
system.cpu.l2cache.tags.replacements 105931 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
system.cpu.l2cache.tags.replacements 105999 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits
system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits
system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses
system.cpu.l2cache.overall_misses::total 179970 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -572,8 +572,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks
system.cpu.l2cache.writebacks::total 98091 # number of writebacks
system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
system.cpu.l2cache.writebacks::total 98156 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

16
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
View file

@ -17,7 +17,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
@ -327,8 +327,8 @@ voltage_domain=system.voltage_domain
[system.e820_table]
type=X86E820Table
children=entries0 entries1 entries2
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
[system.e820_table.entries0]
type=X86E820Entry
@ -348,6 +348,12 @@ addr=1048576
range_type=1
size=133169152
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
range_type=2
size=65536
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
@ -1016,7 +1022,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-x86.img
image_file=/scratch/andreas/m5/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1036,7 +1042,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/scratch/andreas/m5/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

1
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
View file

@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: Tried to clear PCI interrupt 14
warn: Unknown mouse command 0xe1.

12
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout
Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:21:20
gem5 started Sep 22 2013 06:25:04
gem5 executing on zizzer
gem5 compiled Oct 1 2013 21:55:52
gem5 started Oct 1 2013 22:03:55
gem5 executing on steam
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5196173457000 because m5_exit instruction encountered
Exiting @ tick 5192277855000 because m5_exit instruction encountered

1925
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

File diff suppressed because it is too large Load diff