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Handle access to ASI_QUEUE

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Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
This commit is contained in:
Ali Saidi 2006-12-06 19:25:53 -05:00
parent ecbb8debf6
commit 03be92f23b
6 changed files with 214 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/arch/sparc/asi.cc
View file

@ -256,6 +256,13 @@ namespace SparcISA
return asi == ASI_QUEUE; return asi == ASI_QUEUE;
} }
bool AsiIsInterrupt(ASI asi)
{
return asi == ASI_SWVR_INTR_RECEIVE ||
asi == ASI_SWVR_UDB_INTR_W ||
asi == ASI_SWVR_UDB_INTR_R ;
}
bool AsiIsMmu(ASI asi) bool AsiIsMmu(ASI asi)
{ {
return asi == ASI_MMU || return asi == ASI_MMU ||

1
src/arch/sparc/asi.hh
View file

@ -268,6 +268,7 @@ namespace SparcISA
bool AsiIsPriv(ASI); bool AsiIsPriv(ASI);
bool AsiIsHPriv(ASI); bool AsiIsHPriv(ASI);
bool AsiIsReg(ASI); bool AsiIsReg(ASI);
bool AsiIsInterrupt(ASI);
}; };

74
src/arch/sparc/miscregfile.cc
View file

@ -269,7 +269,22 @@ MiscReg MiscRegFile::readReg(int miscReg)
return scratchPad[6]; return scratchPad[6];
case MISCREG_SCRATCHPAD_R7: case MISCREG_SCRATCHPAD_R7:
return scratchPad[7]; return scratchPad[7];
case MISCREG_QUEUE_CPU_MONDO_HEAD:
return cpu_mondo_head;
case MISCREG_QUEUE_CPU_MONDO_TAIL:
return cpu_mondo_tail;
case MISCREG_QUEUE_DEV_MONDO_HEAD:
return dev_mondo_head;
case MISCREG_QUEUE_DEV_MONDO_TAIL:
return dev_mondo_tail;
case MISCREG_QUEUE_RES_ERROR_HEAD:
return res_error_head;
case MISCREG_QUEUE_RES_ERROR_TAIL:
return res_error_tail;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
return nres_error_head;
case MISCREG_QUEUE_NRES_ERROR_TAIL:
return nres_error_tail;
default: default:
panic("Miscellaneous register %d not implemented\n", miscReg); panic("Miscellaneous register %d not implemented\n", miscReg);
} }
@ -310,6 +325,14 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_HVER: case MISCREG_HVER:
case MISCREG_STRAND_STS_REG: case MISCREG_STRAND_STS_REG:
case MISCREG_HSTICK_CMPR: case MISCREG_HSTICK_CMPR:
case MISCREG_QUEUE_CPU_MONDO_HEAD:
case MISCREG_QUEUE_CPU_MONDO_TAIL:
case MISCREG_QUEUE_DEV_MONDO_HEAD:
case MISCREG_QUEUE_DEV_MONDO_TAIL:
case MISCREG_QUEUE_RES_ERROR_HEAD:
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM #if FULL_SYSTEM
return readFSRegWithEffect(miscReg, tc); return readFSRegWithEffect(miscReg, tc);
#else #else
@ -522,6 +545,30 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
case MISCREG_SCRATCHPAD_R7: case MISCREG_SCRATCHPAD_R7:
scratchPad[7] = val; scratchPad[7] = val;
break; break;
case MISCREG_QUEUE_CPU_MONDO_HEAD:
cpu_mondo_head = val;
break;
case MISCREG_QUEUE_CPU_MONDO_TAIL:
cpu_mondo_tail = val;
break;
case MISCREG_QUEUE_DEV_MONDO_HEAD:
dev_mondo_head = val;
break;
case MISCREG_QUEUE_DEV_MONDO_TAIL:
dev_mondo_tail = val;
break;
case MISCREG_QUEUE_RES_ERROR_HEAD:
res_error_head = val;
break;
case MISCREG_QUEUE_RES_ERROR_TAIL:
res_error_tail = val;
break;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
nres_error_head = val;
break;
case MISCREG_QUEUE_NRES_ERROR_TAIL:
nres_error_tail = val;
break;
default: default:
panic("Miscellaneous register %d not implemented\n", miscReg); panic("Miscellaneous register %d not implemented\n", miscReg);
@ -568,6 +615,14 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_HVER: case MISCREG_HVER:
case MISCREG_STRAND_STS_REG: case MISCREG_STRAND_STS_REG:
case MISCREG_HSTICK_CMPR: case MISCREG_HSTICK_CMPR:
case MISCREG_QUEUE_CPU_MONDO_HEAD:
case MISCREG_QUEUE_CPU_MONDO_TAIL:
case MISCREG_QUEUE_DEV_MONDO_HEAD:
case MISCREG_QUEUE_DEV_MONDO_TAIL:
case MISCREG_QUEUE_RES_ERROR_HEAD:
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM #if FULL_SYSTEM
setFSRegWithEffect(miscReg, val, tc); setFSRegWithEffect(miscReg, val, tc);
return; return;
@ -627,6 +682,14 @@ void MiscRegFile::serialize(std::ostream & os)
SERIALIZE_SCALAR(dTlbSfar); SERIALIZE_SCALAR(dTlbSfar);
SERIALIZE_SCALAR(dTlbTagAccess); SERIALIZE_SCALAR(dTlbTagAccess);
SERIALIZE_ARRAY(scratchPad,8); SERIALIZE_ARRAY(scratchPad,8);
SERIALIZE_SCALAR(cpu_mondo_head);
SERIALIZE_SCALAR(cpu_mondo_tail);
SERIALIZE_SCALAR(dev_mondo_head);
SERIALIZE_SCALAR(dev_mondo_tail);
SERIALIZE_SCALAR(res_error_head);
SERIALIZE_SCALAR(res_error_tail);
SERIALIZE_SCALAR(nres_error_head);
SERIALIZE_SCALAR(nres_error_tail);
} }
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
@ -678,4 +741,11 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
UNSERIALIZE_SCALAR(dTlbSfar); UNSERIALIZE_SCALAR(dTlbSfar);
UNSERIALIZE_SCALAR(dTlbTagAccess); UNSERIALIZE_SCALAR(dTlbTagAccess);
UNSERIALIZE_ARRAY(scratchPad,8); UNSERIALIZE_ARRAY(scratchPad,8);
} UNSERIALIZE_SCALAR(cpu_mondo_head);
UNSERIALIZE_SCALAR(cpu_mondo_tail);
UNSERIALIZE_SCALAR(dev_mondo_head);
UNSERIALIZE_SCALAR(dev_mondo_tail);
UNSERIALIZE_SCALAR(res_error_head);
UNSERIALIZE_SCALAR(res_error_tail);
UNSERIALIZE_SCALAR(nres_error_head);
UNSERIALIZE_SCALAR(nres_error_tail);}

20
src/arch/sparc/miscregfile.hh
View file

@ -126,6 +126,17 @@ namespace SparcISA
MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R5,
MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R6,
MISCREG_SCRATCHPAD_R7, MISCREG_SCRATCHPAD_R7,
/* CPU Queue Registers */
MISCREG_QUEUE_CPU_MONDO_HEAD,
MISCREG_QUEUE_CPU_MONDO_TAIL,
MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
MISCREG_QUEUE_DEV_MONDO_TAIL,
MISCREG_QUEUE_RES_ERROR_HEAD,
MISCREG_QUEUE_RES_ERROR_TAIL,
MISCREG_QUEUE_NRES_ERROR_HEAD,
MISCREG_QUEUE_NRES_ERROR_TAIL,
MISCREG_NUMMISCREGS MISCREG_NUMMISCREGS
}; };
@ -210,6 +221,15 @@ namespace SparcISA
uint64_t scratchPad[8]; uint64_t scratchPad[8];
uint64_t cpu_mondo_head;
uint64_t cpu_mondo_tail;
uint64_t dev_mondo_head;
uint64_t dev_mondo_tail;
uint64_t res_error_head;
uint64_t res_error_tail;
uint64_t nres_error_head;
uint64_t nres_error_tail;
// These need to check the int_dis field and if 0 then // These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu // set appropriate bit in softint and checkinterrutps on the cpu
#if FULL_SYSTEM #if FULL_SYSTEM

86
src/arch/sparc/regfile.cc
View file

@ -254,6 +254,92 @@ void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
// FSR // FSR
dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR)); dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
//Strand Status Register
dest->setMiscReg(MISCREG_STRAND_STS_REG,
src->readMiscReg(MISCREG_STRAND_STS_REG));
// MMU Registers
dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
src->readMiscReg(MISCREG_MMU_P_CONTEXT));
dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
src->readMiscReg(MISCREG_MMU_S_CONTEXT));
dest->setMiscReg(MISCREG_MMU_PART_ID,
src->readMiscReg(MISCREG_MMU_PART_ID));
dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
src->readMiscReg(MISCREG_MMU_LSU_CTRL));
dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
// Scratchpad Registers
dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
src->readMiscReg(MISCREG_SCRATCHPAD_R0));
dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
src->readMiscReg(MISCREG_SCRATCHPAD_R1));
dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
src->readMiscReg(MISCREG_SCRATCHPAD_R2));
dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
src->readMiscReg(MISCREG_SCRATCHPAD_R3));
dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
src->readMiscReg(MISCREG_SCRATCHPAD_R4));
dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
src->readMiscReg(MISCREG_SCRATCHPAD_R5));
dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
src->readMiscReg(MISCREG_SCRATCHPAD_R6));
dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
src->readMiscReg(MISCREG_SCRATCHPAD_R7));
// Queue Registers
dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
} }
void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest) void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)

28
src/arch/sparc/tlb.cc
View file

@ -31,6 +31,7 @@
#include "arch/sparc/asi.hh" #include "arch/sparc/asi.hh"
#include "arch/sparc/miscregfile.hh" #include "arch/sparc/miscregfile.hh"
#include "arch/sparc/tlb.hh" #include "arch/sparc/tlb.hh"
#include "base/bitfield.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
@ -479,11 +480,15 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
panic("Twin ASIs not supported\n"); panic("Twin ASIs not supported\n");
if (AsiIsPartialStore(asi)) if (AsiIsPartialStore(asi))
panic("Partial Store ASIs not supported\n"); panic("Partial Store ASIs not supported\n");
if (AsiIsInterrupt(asi))
panic("Interrupt ASIs not supported\n");
if (AsiIsMmu(asi)) if (AsiIsMmu(asi))
goto handleMmuRegAccess; goto handleMmuRegAccess;
if (AsiIsScratchPad(asi)) if (AsiIsScratchPad(asi))
goto handleScratchRegAccess; goto handleScratchRegAccess;
if (AsiIsQueue(asi))
goto handleQueueRegAccess;
if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
panic("Accessing ASI %#X. Should we?\n", asi); panic("Accessing ASI %#X. Should we?\n", asi);
@ -542,6 +547,20 @@ handleScratchRegAccess:
writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException; return new DataAccessException;
} }
goto regAccessOk;
handleQueueRegAccess:
if (!priv && !hpriv) {
writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
return new PrivilegedAction;
}
if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
goto regAccessOk;
regAccessOk:
handleMmuRegAccess: handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
req->setMmapedIpr(true); req->setMmapedIpr(true);
@ -575,6 +594,10 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
goto doMmuReadError; goto doMmuReadError;
} }
break; break;
case ASI_QUEUE:
pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
(va >> 4) - 0x3c));
break;
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
assert(va == 0); assert(va == 0);
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
@ -672,6 +695,11 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
goto doMmuWriteError; goto doMmuWriteError;
} }
break; break;
case ASI_QUEUE:
assert(mbits(va,13,6) == va);
tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
(va >> 4) - 0x3c, data);
break;
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
assert(va == 0); assert(va == 0);
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);