arm: ISA X31 destination register fix
This patch substituted the zero register for X31 used as a destination register. This prevents false dependencies based on X31.
This commit is contained in:
Andrew Bardsley
parent
ee68c2b302
commit
035a82ee2c
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010-2013 ARM Limited
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* Copyright (c) 2010-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -510,6 +510,13 @@ makeSP(IntRegIndex reg)
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return reg;
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}
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static inline IntRegIndex
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makeZero(IntRegIndex reg)
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{
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if (reg == INTREG_X31)
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reg = INTREG_ZERO;
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return reg;
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}
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static inline bool
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isSP(IntRegIndex reg)
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@ -1,4 +1,4 @@
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// Copyright (c) 2011-2013 ARM Limited
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// Copyright (c) 2011-2014 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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@ -63,6 +63,7 @@ namespace Aarch64
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{
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IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
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IntRegIndex rdsp = makeSP(rd);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
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IntRegIndex rnsp = makeSP(rn);
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@ -79,9 +80,9 @@ namespace Aarch64
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uint64_t immhi = bits(machInst, 23, 5);
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uint64_t imm = (immlo << 0) | (immhi << 2);
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if (bits(machInst, 31) == 0)
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return new AdrXImm(machInst, rd, INTREG_ZERO, sext<21>(imm));
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return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm));
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else
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return new AdrpXImm(machInst, rd, INTREG_ZERO,
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return new AdrpXImm(machInst, rdzr, INTREG_ZERO,
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sext<33>(imm << 12));
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}
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case 0x2:
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@ -100,11 +101,11 @@ namespace Aarch64
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case 0x0:
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return new AddXImm(machInst, rdsp, rnsp, imm);
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case 0x1:
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return new AddXImmCc(machInst, rd, rnsp, imm);
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return new AddXImmCc(machInst, rdzr, rnsp, imm);
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case 0x2:
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return new SubXImm(machInst, rdsp, rnsp, imm);
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case 0x3:
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return new SubXImmCc(machInst, rd, rnsp, imm);
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return new SubXImmCc(machInst, rdzr, rnsp, imm);
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}
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}
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case 0x4:
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@ -146,23 +147,24 @@ namespace Aarch64
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case 0x2:
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return new EorXImm(machInst, rdsp, rn, imm);
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case 0x3:
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return new AndXImmCc(machInst, rd, rn, imm);
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return new AndXImmCc(machInst, rdzr, rn, imm);
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}
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}
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case 0x5:
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{
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IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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uint32_t imm16 = bits(machInst, 20, 5);
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uint32_t hw = bits(machInst, 22, 21);
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switch (opc) {
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case 0x0:
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return new Movn(machInst, rd, imm16, hw * 16);
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return new Movn(machInst, rdzr, imm16, hw * 16);
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case 0x1:
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return new Unknown64(machInst);
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case 0x2:
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return new Movz(machInst, rd, imm16, hw * 16);
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return new Movz(machInst, rdzr, imm16, hw * 16);
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case 0x3:
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return new Movk(machInst, rd, imm16, hw * 16);
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return new Movk(machInst, rdzr, imm16, hw * 16);
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}
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}
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case 0x6:
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@ -170,11 +172,11 @@ namespace Aarch64
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return new Unknown64(machInst);
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switch (opc) {
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case 0x0:
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return new Sbfm64(machInst, rd, rn, immr, imms);
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return new Sbfm64(machInst, rdzr, rn, immr, imms);
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case 0x1:
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return new Bfm64(machInst, rd, rn, immr, imms);
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return new Bfm64(machInst, rdzr, rn, immr, imms);
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case 0x2:
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return new Ubfm64(machInst, rd, rn, immr, imms);
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return new Ubfm64(machInst, rdzr, rn, immr, imms);
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case 0x3:
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return new Unknown64(machInst);
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}
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@ -184,7 +186,7 @@ namespace Aarch64
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if (opc || bits(machInst, 21))
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return new Unknown64(machInst);
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else
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return new Extr64(machInst, rd, rn, rm, imms);
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return new Extr64(machInst, rdzr, rn, rm, imms);
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}
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}
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return new FailUnimplemented("Unhandled Case8", machInst);
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@ -1026,26 +1028,27 @@ namespace Aarch64
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if (!sf && (imm6 & 0x20))
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return new Unknown64(machInst);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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switch (switchVal) {
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case 0x0:
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return new AndXSReg(machInst, rd, rn, rm, imm6, type);
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return new AndXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x1:
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return new BicXSReg(machInst, rd, rn, rm, imm6, type);
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return new BicXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x2:
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return new OrrXSReg(machInst, rd, rn, rm, imm6, type);
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return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x3:
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return new OrnXSReg(machInst, rd, rn, rm, imm6, type);
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return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x4:
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return new EorXSReg(machInst, rd, rn, rm, imm6, type);
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return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x5:
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return new EonXSReg(machInst, rd, rn, rm, imm6, type);
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return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x6:
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return new AndXSRegCc(machInst, rd, rn, rm, imm6, type);
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return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
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case 0x7:
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return new BicXSRegCc(machInst, rd, rn, rm, imm6, type);
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return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
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}
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}
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case 0x1:
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@ -1060,17 +1063,18 @@ namespace Aarch64
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if (!bits(machInst, 31) && bits(imm6, 5))
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return new Unknown64(machInst);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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switch (switchVal) {
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case 0x0:
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return new AddXSReg(machInst, rd, rn, rm, imm6, type);
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return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x1:
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return new AddXSRegCc(machInst, rd, rn, rm, imm6, type);
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return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
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case 0x2:
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return new SubXSReg(machInst, rd, rn, rm, imm6, type);
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return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
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case 0x3:
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return new SubXSRegCc(machInst, rd, rn, rm, imm6, type);
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return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
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}
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} else {
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if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
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@ -1080,6 +1084,7 @@ namespace Aarch64
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uint8_t imm3 = bits(machInst, 12, 10);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdsp = makeSP(rd);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex rnsp = makeSP(rn);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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@ -1088,11 +1093,11 @@ namespace Aarch64
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case 0x0:
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return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
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case 0x1:
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return new AddXERegCc(machInst, rd, rnsp, rm, type, imm3);
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return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
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case 0x2:
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return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
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case 0x3:
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return new SubXERegCc(machInst, rd, rnsp, rm, type, imm3);
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return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
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}
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}
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}
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@ -1101,6 +1106,7 @@ namespace Aarch64
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if (bits(machInst, 21) == 1)
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return new Unknown64(machInst);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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switch (bits(machInst, 23, 22)) {
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@ -1111,13 +1117,13 @@ namespace Aarch64
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uint8_t switchVal = bits(machInst, 30, 29);
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switch (switchVal) {
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case 0x0:
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return new AdcXSReg(machInst, rd, rn, rm, 0, LSL);
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return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL);
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case 0x1:
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return new AdcXSRegCc(machInst, rd, rn, rm, 0, LSL);
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return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
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case 0x2:
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return new SbcXSReg(machInst, rd, rn, rm, 0, LSL);
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return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL);
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case 0x3:
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return new SbcXSRegCc(machInst, rd, rn, rm, 0, LSL);
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return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
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}
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}
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case 0x1:
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@ -1157,19 +1163,20 @@ namespace Aarch64
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uint8_t switchVal = (bits(machInst, 10) << 0) |
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(bits(machInst, 30) << 1);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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ConditionCode cond =
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(ConditionCode)(uint8_t)bits(machInst, 15, 12);
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switch (switchVal) {
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case 0x0:
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return new Csel64(machInst, rd, rn, rm, cond);
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return new Csel64(machInst, rdzr, rn, rm, cond);
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case 0x1:
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return new Csinc64(machInst, rd, rn, rm, cond);
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return new Csinc64(machInst, rdzr, rn, rm, cond);
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case 0x2:
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return new Csinv64(machInst, rd, rn, rm, cond);
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return new Csinv64(machInst, rdzr, rn, rm, cond);
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case 0x3:
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return new Csneg64(machInst, rd, rn, rm, cond);
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return new Csneg64(machInst, rdzr, rn, rm, cond);
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}
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}
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case 0x3:
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@ -1179,17 +1186,17 @@ namespace Aarch64
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uint8_t switchVal = bits(machInst, 15, 10);
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switch (switchVal) {
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case 0x2:
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return new Udiv64(machInst, rd, rn, rm);
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return new Udiv64(machInst, rdzr, rn, rm);
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case 0x3:
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return new Sdiv64(machInst, rd, rn, rm);
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return new Sdiv64(machInst, rdzr, rn, rm);
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case 0x8:
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return new Lslv64(machInst, rd, rn, rm);
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return new Lslv64(machInst, rdzr, rn, rm);
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case 0x9:
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return new Lsrv64(machInst, rd, rn, rm);
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return new Lsrv64(machInst, rdzr, rn, rm);
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case 0xa:
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return new Asrv64(machInst, rd, rn, rm);
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return new Asrv64(machInst, rdzr, rn, rm);
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case 0xb:
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return new Rorv64(machInst, rd, rn, rm);
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return new Rorv64(machInst, rdzr, rn, rm);
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default:
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return new Unknown64(machInst);
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}
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@ -1201,22 +1208,22 @@ namespace Aarch64
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uint8_t switchVal = bits(machInst, 15, 10);
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switch (switchVal) {
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case 0x0:
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return new Rbit64(machInst, rd, rn);
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return new Rbit64(machInst, rdzr, rn);
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case 0x1:
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return new Rev1664(machInst, rd, rn);
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return new Rev1664(machInst, rdzr, rn);
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case 0x2:
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if (bits(machInst, 31) == 0)
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return new Rev64(machInst, rd, rn);
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return new Rev64(machInst, rdzr, rn);
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else
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return new Rev3264(machInst, rd, rn);
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return new Rev3264(machInst, rdzr, rn);
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case 0x3:
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if (bits(machInst, 31) != 1)
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return new Unknown64(machInst);
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return new Rev64(machInst, rd, rn);
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return new Rev64(machInst, rdzr, rn);
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case 0x4:
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return new Clz64(machInst, rd, rn);
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return new Clz64(machInst, rdzr, rn);
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case 0x5:
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return new Cls64(machInst, rd, rn);
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return new Cls64(machInst, rdzr, rn);
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}
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}
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}
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@ -1227,33 +1234,34 @@ namespace Aarch64
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(bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0))
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return new Unknown64(machInst);
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IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
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IntRegIndex rdzr = makeZero(rd);
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IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
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IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
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IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
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switch (bits(machInst, 23, 21)) {
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case 0x0:
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if (bits(machInst, 15) == 0)
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return new Madd64(machInst, rd, ra, rn, rm);
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return new Madd64(machInst, rdzr, ra, rn, rm);
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else
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return new Msub64(machInst, rd, ra, rn, rm);
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return new Msub64(machInst, rdzr, ra, rn, rm);
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case 0x1:
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if (bits(machInst, 15) == 0)
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return new Smaddl64(machInst, rd, ra, rn, rm);
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return new Smaddl64(machInst, rdzr, ra, rn, rm);
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else
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return new Smsubl64(machInst, rd, ra, rn, rm);
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return new Smsubl64(machInst, rdzr, ra, rn, rm);
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case 0x2:
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if (bits(machInst, 15) != 0)
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return new Unknown64(machInst);
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return new Smulh64(machInst, rd, rn, rm);
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return new Smulh64(machInst, rdzr, rn, rm);
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case 0x5:
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if (bits(machInst, 15) == 0)
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return new Umaddl64(machInst, rd, ra, rn, rm);
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return new Umaddl64(machInst, rdzr, ra, rn, rm);
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else
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return new Umsubl64(machInst, rd, ra, rn, rm);
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return new Umsubl64(machInst, rdzr, ra, rn, rm);
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case 0x6:
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if (bits(machInst, 15) != 0)
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return new Unknown64(machInst);
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return new Umulh64(machInst, rd, rn, rm);
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return new Umulh64(machInst, rdzr, rn, rm);
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default:
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return new Unknown64(machInst);
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}
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