the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
This commit is contained in:
parent
b45219e7ae
commit
032ea9b2db
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@ -34,19 +34,45 @@
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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namespace SparcISA
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namespace SparcISA
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{
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{
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enum interrupts_t {
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trap_level_zero,
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hstick_match,
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interrupt_vector,
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cpu_mondo,
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dev_mondo,
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resumable_error,
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soft_interrupt,
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num_interrupt_types
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};
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class Interrupts
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class Interrupts
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{
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{
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protected:
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private:
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bool interrupts[num_interrupt_types];
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int numPosted;
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public:
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public:
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Interrupts()
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Interrupts()
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{
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{
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for (int i = 0; i < num_interrupt_types; ++i) {
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interrupts[i] = false;
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}
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numPosted = 0;
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}
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}
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void post(int int_type)
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{
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if (int_type < 0 || int_type >= num_interrupt_types)
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panic("posting unknown interrupt!\n");
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interrupts[int_type] = true;
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++numPosted;
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}
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void post(int int_num, int index)
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void post(int int_num, int index)
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{
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{
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@ -64,9 +90,7 @@ namespace SparcISA
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bool check_interrupts(ThreadContext * tc) const
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bool check_interrupts(ThreadContext * tc) const
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{
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{
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// so far only handle softint interrupts
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if (numPosted)
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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if (int_level)
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return true;
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return true;
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else
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else
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return false;
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return false;
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@ -74,14 +98,99 @@ namespace SparcISA
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Fault getInterrupt(ThreadContext * tc)
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Fault getInterrupt(ThreadContext * tc)
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{
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{
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int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
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int pstate = tc->readMiscReg(MISCREG_PSTATE);
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bool ie = pstate & PSTATE::ie;
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// THESE ARE IN ORDER OF PRIORITY
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// since there are early returns, and the highest
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// priority interrupts should get serviced,
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// it is v. important that new interrupts are inserted
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// in the right order of processing
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if (hpstate & HPSTATE::hpriv) {
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if (ie) {
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if (interrupts[hstick_match]) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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if (interrupts[interrupt_vector]) {
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed THIS YET
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return NoFault;
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}
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}
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} else {
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if (interrupts[trap_level_zero]) {
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//HAVEN'T IMPLed YET
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if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
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interrupts[trap_level_zero] = false;
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--numPosted;
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return NoFault;
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}
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}
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if (interrupts[hstick_match]) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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if (ie) {
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if (interrupts[cpu_mondo]) {
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interrupts[cpu_mondo] = false;
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--numPosted;
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return new CpuMondo;
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}
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if (interrupts[dev_mondo]) {
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interrupts[dev_mondo] = false;
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--numPosted;
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return new DevMondo;
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}
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if (interrupts[soft_interrupt]) {
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int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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// it seems that interrupt vectors are right in
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// the middle of interrupt levels with regard to
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// priority, so have to check
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if ((il < 6) &&
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interrupts[interrupt_vector]) {
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// may require more details here since there
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// may be lots of interrupts embedded in an
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// platform interrupt vector
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed YET
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return NoFault;
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} else {
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if (il > tc->readMiscReg(MISCREG_PIL)) {
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uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
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uint64_t more = si & ~(1 << (il + 1));
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if (!InterruptLevel(more)) {
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interrupts[soft_interrupt] = false;
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--numPosted;
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}
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return new InterruptLevelN(il);
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}
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}
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}
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if (interrupts[resumable_error]) {
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interrupts[resumable_error] = false;
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--numPosted;
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return new ResumableError;
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}
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}
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}
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return NoFault;
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// conditioning the softint interrups
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// conditioning the softint interrups
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if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) {
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if (tc->readMiscReg(MISCREG_HPSTATE) & HPSTATE::hpriv) {
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// if running in privileged mode, then pend the interrupt
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// if running in privileged mode, then pend the interrupt
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return NoFault;
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return NoFault;
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} else {
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} else {
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
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if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
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!(tc->readMiscReg(MISCREG_PSTATE) & ie)) {
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!(tc->readMiscReg(MISCREG_PSTATE) & PSTATE::ie)) {
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// if PIL or no interrupt enabled, then pend the interrupt
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// if PIL or no interrupt enabled, then pend the interrupt
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return NoFault;
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return NoFault;
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} else {
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} else {
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@ -38,105 +38,105 @@ using namespace SparcISA;
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void
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void
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MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext *tc)
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ThreadContext *tc)
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{
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{
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int64_t time;
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int64_t time;
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switch (miscReg) {
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switch (miscReg) {
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/* Full system only ASRs */
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/* Full system only ASRs */
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case MISCREG_SOFTINT:
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case MISCREG_SOFTINT:
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// Check if we are going to interrupt because of something
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// Check if we are going to interrupt because of something
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setReg(miscReg, val);
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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warn("Writing to softint not really supported, writing: %#x\n", val);
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warn("Writing to softint not really supported, writing: %#x\n", val);
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break;
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break;
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_CLR:
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return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
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return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
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case MISCREG_SOFTINT_SET:
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case MISCREG_SOFTINT_SET:
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return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
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return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
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case MISCREG_TICK_CMPR:
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case MISCREG_TICK_CMPR:
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if (tickCompare == NULL)
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if (tickCompare == NULL)
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tickCompare = new TickCompareEvent(this, tc);
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tickCompare = new TickCompareEvent(this, tc);
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setReg(miscReg, val);
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setReg(miscReg, val);
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if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
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if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
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tickCompare->deschedule();
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tickCompare->deschedule();
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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if (!(tick_cmpr & ~mask(63)) && time > 0)
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if (!(tick_cmpr & ~mask(63)) && time > 0)
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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panic("writing to TICK compare register %#X\n", val);
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panic("writing to TICK compare register %#X\n", val);
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break;
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break;
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case MISCREG_STICK_CMPR:
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case MISCREG_STICK_CMPR:
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if (sTickCompare == NULL)
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if (sTickCompare == NULL)
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sTickCompare = new STickCompareEvent(this, tc);
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sTickCompare = new STickCompareEvent(this, tc);
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setReg(miscReg, val);
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setReg(miscReg, val);
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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sTickCompare->deschedule();
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sTickCompare->deschedule();
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time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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tc->getCpuPtr()->instCount();
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if (!(stick_cmpr & ~mask(63)) && time > 0)
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if (!(stick_cmpr & ~mask(63)) && time > 0)
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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break;
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case MISCREG_PSTATE:
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case MISCREG_PSTATE:
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if (val & ie && !(pstate & ie)) {
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if (val & ie && !(pstate & ie)) {
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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}
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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case MISCREG_PIL:
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case MISCREG_PIL:
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if (val < pil) {
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if (val < pil) {
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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}
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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break;
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break;
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case MISCREG_HVER:
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case MISCREG_HVER:
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panic("Shouldn't be writing HVER\n");
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panic("Shouldn't be writing HVER\n");
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|
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case MISCREG_HTBA:
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case MISCREG_HTBA:
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// clear lower 7 bits on writes.
|
// clear lower 7 bits on writes.
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setReg(miscReg, val & ULL(~0x7FFF));
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setReg(miscReg, val & ULL(~0x7FFF));
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break;
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break;
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
|
case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
|
case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
|
case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
|
case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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setReg(miscReg, val);
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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break;
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break;
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|
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case MISCREG_HSTICK_CMPR:
|
case MISCREG_HSTICK_CMPR:
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if (hSTickCompare == NULL)
|
if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
|
hSTickCompare = new HSTickCompareEvent(this, tc);
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setReg(miscReg, val);
|
setReg(miscReg, val);
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if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
|
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
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hSTickCompare->deschedule();
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hSTickCompare->deschedule();
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time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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tc->getCpuPtr()->instCount();
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if (!(hstick_cmpr & ~mask(63)) && time > 0)
|
if (!(hstick_cmpr & ~mask(63)) && time > 0)
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hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
|
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
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DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
|
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
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break;
|
break;
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||||||
|
|
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case MISCREG_HPSTATE:
|
case MISCREG_HPSTATE:
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// T1000 spec says impl. dependent val must always be 1
|
// T1000 spec says impl. dependent val must always be 1
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setReg(miscReg, val | id);
|
setReg(miscReg, val | id);
|
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break;
|
break;
|
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case MISCREG_HTSTATE:
|
case MISCREG_HTSTATE:
|
||||||
case MISCREG_STRAND_STS_REG:
|
case MISCREG_STRAND_STS_REG:
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setReg(miscReg, val);
|
setReg(miscReg, val);
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||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
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panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
|
panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -144,7 +144,7 @@ MiscReg
|
||||||
MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
|
MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
|
||||||
{
|
{
|
||||||
switch (miscReg) {
|
switch (miscReg) {
|
||||||
/* Privileged registers. */
|
/* Privileged registers. */
|
||||||
case MISCREG_QUEUE_CPU_MONDO_HEAD:
|
case MISCREG_QUEUE_CPU_MONDO_HEAD:
|
||||||
case MISCREG_QUEUE_CPU_MONDO_TAIL:
|
case MISCREG_QUEUE_CPU_MONDO_TAIL:
|
||||||
case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
||||||
|
@ -174,12 +174,12 @@ MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
In Niagra STICK==TICK so this isn't needed
|
In Niagra STICK==TICK so this isn't needed
|
||||||
case MISCREG_STICK:
|
case MISCREG_STICK:
|
||||||
SparcSystem *sys;
|
SparcSystem *sys;
|
||||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||||
assert(sys != NULL);
|
assert(sys != NULL);
|
||||||
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
|
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
@ -198,12 +198,13 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
|
||||||
// more
|
// more
|
||||||
int ticks;
|
int ticks;
|
||||||
ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
|
ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
|
||||||
tc->getCpuPtr()->instCount();
|
tc->getCpuPtr()->instCount();
|
||||||
assert(ticks >= 0 && "stick compare missed interrupt cycle");
|
assert(ticks >= 0 && "stick compare missed interrupt cycle");
|
||||||
|
|
||||||
if (ticks == 0) {
|
if (ticks == 0) {
|
||||||
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
|
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
|
||||||
(stick_cmpr & mask(63)));
|
(stick_cmpr & mask(63)));
|
||||||
|
tc->getCpuPtr()->post_interrupt(soft_interrupt);
|
||||||
tc->getCpuPtr()->checkInterrupts = true;
|
tc->getCpuPtr()->checkInterrupts = true;
|
||||||
softint |= ULL(1) << 16;
|
softint |= ULL(1) << 16;
|
||||||
} else
|
} else
|
||||||
|
@ -218,12 +219,13 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
|
||||||
// more
|
// more
|
||||||
int ticks;
|
int ticks;
|
||||||
ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
|
ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
|
||||||
tc->getCpuPtr()->instCount();
|
tc->getCpuPtr()->instCount();
|
||||||
assert(ticks >= 0 && "hstick compare missed interrupt cycle");
|
assert(ticks >= 0 && "hstick compare missed interrupt cycle");
|
||||||
|
|
||||||
if (ticks == 0) {
|
if (ticks == 0) {
|
||||||
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
|
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
|
||||||
(stick_cmpr & mask(63)));
|
(stick_cmpr & mask(63)));
|
||||||
|
tc->getCpuPtr()->post_interrupt(hstick_match);
|
||||||
tc->getCpuPtr()->checkInterrupts = true;
|
tc->getCpuPtr()->checkInterrupts = true;
|
||||||
// Need to do something to cause interrupt to happen here !!! @todo
|
// Need to do something to cause interrupt to happen here !!! @todo
|
||||||
} else
|
} else
|
||||||
|
|
|
@ -362,6 +362,12 @@ BaseCPU::ProfileEvent::process()
|
||||||
schedule(curTick + interval);
|
schedule(curTick + interval);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
BaseCPU::post_interrupt(int int_type)
|
||||||
|
{
|
||||||
|
interrupts.post(int_type);
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
BaseCPU::post_interrupt(int int_num, int index)
|
BaseCPU::post_interrupt(int int_num, int index)
|
||||||
{
|
{
|
||||||
|
|
|
@ -102,6 +102,7 @@ class BaseCPU : public MemObject
|
||||||
TheISA::Interrupts interrupts;
|
TheISA::Interrupts interrupts;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
virtual void post_interrupt(int int_type);
|
||||||
virtual void post_interrupt(int int_num, int index);
|
virtual void post_interrupt(int int_num, int index);
|
||||||
virtual void clear_interrupt(int int_num, int index);
|
virtual void clear_interrupt(int int_num, int index);
|
||||||
virtual void clear_interrupts();
|
virtual void clear_interrupts();
|
||||||
|
|
Loading…
Reference in a new issue