the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
This commit is contained in:
parent
b45219e7ae
commit
032ea9b2db
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@ -34,19 +34,45 @@
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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namespace SparcISA
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namespace SparcISA
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{
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{
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enum interrupts_t {
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trap_level_zero,
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hstick_match,
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interrupt_vector,
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cpu_mondo,
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dev_mondo,
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resumable_error,
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soft_interrupt,
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num_interrupt_types
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};
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class Interrupts
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class Interrupts
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{
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{
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protected:
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private:
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bool interrupts[num_interrupt_types];
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int numPosted;
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public:
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public:
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Interrupts()
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Interrupts()
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{
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{
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for (int i = 0; i < num_interrupt_types; ++i) {
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interrupts[i] = false;
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}
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}
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numPosted = 0;
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}
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void post(int int_type)
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{
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if (int_type < 0 || int_type >= num_interrupt_types)
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panic("posting unknown interrupt!\n");
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interrupts[int_type] = true;
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++numPosted;
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}
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void post(int int_num, int index)
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void post(int int_num, int index)
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{
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{
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@ -64,9 +90,7 @@ namespace SparcISA
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bool check_interrupts(ThreadContext * tc) const
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bool check_interrupts(ThreadContext * tc) const
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{
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{
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// so far only handle softint interrupts
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if (numPosted)
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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if (int_level)
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return true;
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return true;
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else
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else
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return false;
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return false;
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@ -74,14 +98,99 @@ namespace SparcISA
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Fault getInterrupt(ThreadContext * tc)
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Fault getInterrupt(ThreadContext * tc)
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{
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{
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int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
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int pstate = tc->readMiscReg(MISCREG_PSTATE);
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bool ie = pstate & PSTATE::ie;
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// THESE ARE IN ORDER OF PRIORITY
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// since there are early returns, and the highest
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// priority interrupts should get serviced,
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// it is v. important that new interrupts are inserted
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// in the right order of processing
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if (hpstate & HPSTATE::hpriv) {
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if (ie) {
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if (interrupts[hstick_match]) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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if (interrupts[interrupt_vector]) {
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed THIS YET
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return NoFault;
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}
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}
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} else {
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if (interrupts[trap_level_zero]) {
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//HAVEN'T IMPLed YET
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if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
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interrupts[trap_level_zero] = false;
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--numPosted;
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return NoFault;
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}
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}
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if (interrupts[hstick_match]) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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if (ie) {
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if (interrupts[cpu_mondo]) {
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interrupts[cpu_mondo] = false;
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--numPosted;
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return new CpuMondo;
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}
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if (interrupts[dev_mondo]) {
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interrupts[dev_mondo] = false;
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--numPosted;
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return new DevMondo;
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}
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if (interrupts[soft_interrupt]) {
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int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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// it seems that interrupt vectors are right in
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// the middle of interrupt levels with regard to
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// priority, so have to check
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if ((il < 6) &&
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interrupts[interrupt_vector]) {
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// may require more details here since there
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// may be lots of interrupts embedded in an
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// platform interrupt vector
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed YET
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return NoFault;
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} else {
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if (il > tc->readMiscReg(MISCREG_PIL)) {
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uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
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uint64_t more = si & ~(1 << (il + 1));
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if (!InterruptLevel(more)) {
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interrupts[soft_interrupt] = false;
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--numPosted;
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}
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return new InterruptLevelN(il);
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}
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}
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}
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if (interrupts[resumable_error]) {
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interrupts[resumable_error] = false;
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--numPosted;
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return new ResumableError;
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}
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}
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}
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return NoFault;
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// conditioning the softint interrups
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// conditioning the softint interrups
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if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) {
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if (tc->readMiscReg(MISCREG_HPSTATE) & HPSTATE::hpriv) {
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// if running in privileged mode, then pend the interrupt
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// if running in privileged mode, then pend the interrupt
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return NoFault;
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return NoFault;
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} else {
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} else {
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
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if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
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!(tc->readMiscReg(MISCREG_PSTATE) & ie)) {
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!(tc->readMiscReg(MISCREG_PSTATE) & PSTATE::ie)) {
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// if PIL or no interrupt enabled, then pend the interrupt
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// if PIL or no interrupt enabled, then pend the interrupt
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return NoFault;
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return NoFault;
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} else {
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} else {
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case MISCREG_SOFTINT:
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case MISCREG_SOFTINT:
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// Check if we are going to interrupt because of something
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// Check if we are going to interrupt because of something
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setReg(miscReg, val);
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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warn("Writing to softint not really supported, writing: %#x\n", val);
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warn("Writing to softint not really supported, writing: %#x\n", val);
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break;
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break;
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@ -204,6 +204,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
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if (ticks == 0) {
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if (ticks == 0) {
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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(stick_cmpr & mask(63)));
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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softint |= ULL(1) << 16;
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softint |= ULL(1) << 16;
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} else
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} else
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if (ticks == 0) {
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if (ticks == 0) {
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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(stick_cmpr & mask(63)));
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tc->getCpuPtr()->post_interrupt(hstick_match);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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// Need to do something to cause interrupt to happen here !!! @todo
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// Need to do something to cause interrupt to happen here !!! @todo
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} else
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} else
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schedule(curTick + interval);
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schedule(curTick + interval);
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}
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}
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void
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BaseCPU::post_interrupt(int int_type)
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{
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interrupts.post(int_type);
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}
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void
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void
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BaseCPU::post_interrupt(int int_num, int index)
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BaseCPU::post_interrupt(int int_num, int index)
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{
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{
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TheISA::Interrupts interrupts;
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TheISA::Interrupts interrupts;
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public:
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public:
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virtual void post_interrupt(int int_type);
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virtual void post_interrupt(int int_num, int index);
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virtual void post_interrupt(int int_num, int index);
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virtual void clear_interrupt(int int_num, int index);
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virtual void clear_interrupt(int int_num, int index);
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virtual void clear_interrupts();
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virtual void clear_interrupts();
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