PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1

configs/example/memtest.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -53,7 +53,7 @@ if args:
 # ====================
 
 class L1(BaseCache):
-    latency = 1
+    latency = '1ns'
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
@@ -65,7 +65,7 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    latency = 10
+    latency = '10ns'
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -75,17 +75,15 @@ if options.numtesters > 8:
      print "Error: NUmber of testers limited to 8 because of false sharing"
      sys,exit(1)
 
-if options.timing:
+cpus = [ MemTest(atomic=options.timing, max_loads=options.maxloads,
-     cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50,
+                 percent_functional=50, percent_uncacheable=10,
-                      percent_uncacheable=10, progress_interval=1000)
+                 progress_interval=1000)
-              for i in xrange(options.numtesters) ]
+         for i in xrange(options.numtesters) ]
-else:
+
-     cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50,
-                      percent_uncacheable=10, progress_interval=1000)
-              for i in xrange(options.numtesters) ]
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16))
+                physmem = PhysicalMemory(latency = "50ps"),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
 if options.caches:
@@ -96,7 +94,6 @@ if options.caches:
     # connect l2c to membus
     system.l2c.mem_side = system.membus.port
 
-which_port = 0
 # add L1 caches
 for cpu in cpus:
     if options.caches:
@@ -105,12 +102,7 @@ for cpu in cpus:
          cpu.l1c.mem_side = system.toL2Bus.port
     else:
          cpu.test = system.membus.port
-    if  which_port == 0:
+    system.funcmem.port = cpu.functional
-         system.funcmem.port = cpu.functional
-         which_port = 1
-    else:
-         system.funcmem.functional = cpu.functional
-
 
 # connect memory to membus
 system.physmem.port = system.membus.port

src/mem/physical.cc

@@ -52,7 +52,7 @@ using namespace std;
 using namespace TheISA;
 
 PhysicalMemory::PhysicalMemory(Params *p)
-    : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p)
+    : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p)
 {
     if (params()->addrRange.size() % TheISA::PageBytes != 0)
         panic("Memory Size not divisible by page size\n");
@@ -76,9 +76,10 @@ PhysicalMemory::PhysicalMemory(Params *p)
 void
 PhysicalMemory::init()
 {
-    if (!port)
+    for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
-        panic("PhysicalMemory not connected to anything!");
+        if (*pi)
-    port->sendStatusChange(Port::RangeChange);
+            (*pi)->sendStatusChange(Port::RangeChange);
+    }
 }
 
 PhysicalMemory::~PhysicalMemory()
@@ -335,19 +336,26 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
 Port *
 PhysicalMemory::getPort(const std::string &if_name, int idx)
 {
-    if (if_name == "port" && idx == -1) {
+    if (if_name != "port") {
-        if (port != NULL)
-           panic("PhysicalMemory::getPort: additional port requested to memory!");
-        port = new MemoryPort(name() + "-port", this);
-        return port;
-    } else if (if_name == "functional") {
-        /* special port for functional writes at startup. And for memtester */
-        return new MemoryPort(name() + "-funcport", this);
-    } else {
         panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
     }
+
+    if (idx >= ports.size()) {
+        ports.resize(idx+1);
+    }
+
+    if (ports[idx] != NULL) {
+        panic("PhysicalMemory::getPort: port %d already assigned", idx);
+    }
+
+    MemoryPort *port =
+        new MemoryPort(csprintf("%s-port%d", name(), idx), this);
+
+    ports[idx] = port;
+    return port;
 }
 
+
 void
 PhysicalMemory::recvStatusChange(Port::Status status)
 {
@@ -420,7 +428,11 @@ PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 unsigned int
 PhysicalMemory::drain(Event *de)
 {
-    int count = port->drain(de);
+    int count = 0;
+    for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
+        count += (*pi)->drain(de);
+    }
+
     if (count)
         changeState(Draining);
     else

src/mem/physical.hh

@@ -141,9 +141,10 @@ class PhysicalMemory : public MemObject
     }
 
     uint8_t *pmemAddr;
-    MemoryPort *port;
     int pagePtr;
     Tick lat;
+    std::vector<MemoryPort*> ports;
+    typedef std::vector<MemoryPort*>::iterator PortIterator;
 
   public:
     Addr new_page();

src/python/m5/objects/PhysicalMemory.py

@@ -4,8 +4,7 @@ from MemObject import *
 
 class PhysicalMemory(MemObject):
     type = 'PhysicalMemory'
-    port = Port("the access port")
+    port = VectorPort("the access port")
-    functional = Port("Functional Access Port")
     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
     file = Param.String('', "memory mapped file")
     latency = Param.Latency('1t', "latency of an access")

src/python/swig/pyobject.cc

@@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i)
 
 /**
  * Connect the described MemObject ports.  Called from Python via SWIG.
+ * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports.
  */
 int
 connectPorts(SimObject *o1, const std::string &name1, int i1,

tests/configs/memtest.py

@@ -57,7 +57,8 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
+                physmem = PhysicalMemory(),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
 system.toL2Bus = Bus(clock="500GHz", width=16)
@@ -67,18 +68,12 @@ system.l2c.cpu_side = system.toL2Bus.port
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
-which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    if  which_port == 0:
+    system.funcmem.port = cpu.functional
-         system.funcmem.port = cpu.functional
-         which_port = 1
-    else:
-         system.funcmem.functional = cpu.functional
-
 
 # connect memory to membus
 system.physmem.port = system.membus.port

tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini

@@ -22,7 +22,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.port
+functional=system.funcmem.port[0]
 test=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
@@ -82,7 +82,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[1]
 test=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
@@ -142,7 +142,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[2]
 test=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
@@ -202,7 +202,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[3]
 test=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
@@ -262,7 +262,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[4]
 test=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
@@ -322,7 +322,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[5]
 test=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
@@ -382,7 +382,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[6]
 test=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
@@ -442,7 +442,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[7]
 test=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
@@ -495,8 +495,7 @@ file=
 latency=1
 range=0:134217727
 zero=false
-functional=system.cpu7.functional
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-port=system.cpu0.functional
 
 [system.l2c]
 type=BaseCache
@@ -543,7 +542,7 @@ bus_id=0
 clock=2
 responder_set=false
 width=16
-port=system.l2c.mem_side system.physmem.port
+port=system.l2c.mem_side system.physmem.port[0]
 
 [system.physmem]
 type=PhysicalMemory

tests/quick/50.memtest/ref/alpha/linux/memtest/stdout

@@ -5,15 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 14 2007 16:35:50
+M5 compiled May 18 2007 23:44:20
-M5 started Tue May 15 12:18:46 2007
+M5 started Fri May 18 23:46:19 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
-warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional
-warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional
-warning: overwriting port funcmem.functional value cpu3.functional with cpu4.functional
-warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional
-warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional
-warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 84350509 because Maximum number of loads reached!