Fixes for detailed boot, made cttz and ctlz instructions more compact,
and started cleaning up config files. arch/alpha/isa_desc: Made implementation of cttz and ctlz more compact base/remote_gdb.cc: Added comment about PALcode debugger accesses dev/baddev.cc: dev/baddev.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.cc: dev/tsunami_uart.hh: Cleaned up includes and changed device from FunctionalMemory to PioDevice for detailed boot dev/ns_gige.cc: The ethernet dev uses two BARs, and the first bars size was being set incorrectly. dev/tsunamireg.h: I don't know why we were using the superpage as the PCI memory addr. Changed and works correctly with detailed boot. --HG-- extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
This commit is contained in:
parent
a20f44979a
commit
02f69b94c5
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@ -2119,65 +2119,30 @@ decode OPCODE default Unknown::unknown() {
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0x1c: decode INTFUNC {
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0x1c: decode INTFUNC {
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0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
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0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
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0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
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0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
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0x32: ctlz({{
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0x32: ctlz({{
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uint64_t count = 0;
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uint64_t count = 0;
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uint64_t temp = Rb;
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uint64_t temp = Rb;
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if (temp & ULL(0xffffffff00000000))
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if (temp<63:32>) temp >>= 32; else count += 32;
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temp >>= 32;
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if (temp<31:16>) temp >>= 16; else count += 16;
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else
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if (temp<15:8>) temp >>= 8; else count += 8;
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count += 32;
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if (temp<7:4>) temp >>= 4; else count += 4;
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if (temp & ULL(0xffff0000))
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if (temp<3:2>) temp >>= 2; else count += 2;
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temp >>= 16;
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if (temp<1:1>) temp >>= 1; else count += 1;
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else
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if ((temp<0:0>) != 0x1) count += 1;
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count += 16;
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Rc = count;
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if (temp & ULL(0xff00))
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}}, IntAluOp);
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temp >>= 8;
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else
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count += 8;
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if (temp & ULL(0xf0))
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temp >>= 4;
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else
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count += 4;
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if (temp & ULL(0xC))
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temp >>= 2;
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else
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count += 2;
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if (temp & ULL(0x2))
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temp >>= 1;
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else
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count += 1;
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if ((temp & ULL(0x1)) != 0x1)
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count += 1;
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Rc = count;
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}}, IntAluOp);
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0x33: cttz({{
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0x33: cttz({{
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uint64_t count = 0;
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uint64_t count = 0;
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uint64_t temp = Rb;
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uint64_t temp = Rb;
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if (!(temp & ULL(0x00000000ffffffff))) {
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if (!(temp<31:0>)) { temp >>= 32; count += 32; }
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temp >>= 32;
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if (!(temp<15:0>)) { temp >>= 16; count += 16; }
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count += 32;
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if (!(temp<7:0>)) { temp >>= 8; count += 8; }
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}
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if (!(temp<3:0>)) { temp >>= 4; count += 4; }
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if (!(temp & ULL(0x0000ffff))) {
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if (!(temp<1:0>)) { temp >>= 2; count += 2; }
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temp >>= 16;
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if (!(temp<0:0> & ULL(0x1))) count += 1;
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count += 16;
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Rc = count;
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}
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}}, IntAluOp);
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if (!(temp & ULL(0x00ff))) {
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temp >>= 8;
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count += 8;
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}
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if (!(temp & ULL(0x0f))) {
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temp >>= 4;
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count += 4;
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}
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if (!(temp & ULL(0x3))) {
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temp >>= 2;
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count += 2;
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}
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if (!(temp & ULL(0x1)))
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count += 1;
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Rc = count;
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}}, IntAluOp);
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format FailUnimpl {
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format FailUnimpl {
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0x30: ctpop();
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0x30: ctpop();
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@ -344,6 +344,13 @@ RemoteGDB::acc(Addr va, size_t len)
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}
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}
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}
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}
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/**
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* This code says that all accesses to palcode (instruction and data)
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* are valid since there isn't a va->pa mapping because palcode is
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* accessed physically. At some point this should probably be cleaned up
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* but there is no easy way to do it.
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*/
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if (PC_PAL(va) || va < 0x10000)
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if (PC_PAL(va) || va < 0x10000)
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return true;
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return true;
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@ -36,10 +36,10 @@
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/baddev.hh"
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#include "dev/baddev.hh"
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#include "dev/tsunamireg.h"
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#include "mem/bus/bus.hh"
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#include "dev/tsunami.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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#include "sim/system.hh"
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@ -47,10 +47,17 @@
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using namespace std;
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using namespace std;
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BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
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BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
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const string &devicename)
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HierParams *hier, Bus *bus, const string &devicename)
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: FunctionalMemory(name), addr(a), devname(devicename)
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: PioDevice(name), addr(a), devname(devicename)
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{
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&BadDevice::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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}
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}
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}
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Fault
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Fault
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return No_Fault;
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return No_Fault;
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}
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}
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Tick
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BadDevice::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> addr;
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SimObjectParam<HierParams *> hier;
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SimObjectParam<Bus*> io_bus;
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Param<string> devicename;
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Param<string> devicename;
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END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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@ -81,13 +95,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM(devicename, "Name of device to error on")
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INIT_PARAM(devicename, "Name of device to error on")
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END_INIT_SIM_OBJECT_PARAMS(BadDevice)
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END_INIT_SIM_OBJECT_PARAMS(BadDevice)
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CREATE_SIM_OBJECT(BadDevice)
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CREATE_SIM_OBJECT(BadDevice)
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{
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{
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return new BadDevice(getInstanceName(), addr, mmu, devicename);
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return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, devicename);
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}
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}
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REGISTER_SIM_OBJECT("BadDevice", BadDevice)
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REGISTER_SIM_OBJECT("BadDevice", BadDevice)
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@ -34,7 +34,8 @@
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#ifndef __BADDEV_HH__
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#ifndef __BADDEV_HH__
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#define __BADDEV_HH__
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#define __BADDEV_HH__
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#include "mem/functional_mem/functional_memory.hh"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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/**
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/**
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* BadDevice
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* BadDevice
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@ -42,7 +43,7 @@
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* the user that the kernel they are running has unsupported
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* the user that the kernel they are running has unsupported
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* options (i.e. frame buffer)
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* options (i.e. frame buffer)
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*/
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*/
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class BadDevice : public FunctionalMemory
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class BadDevice : public PioDevice
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{
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{
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private:
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private:
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Addr addr;
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Addr addr;
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@ -56,10 +57,12 @@ class BadDevice : public FunctionalMemory
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* @param name name of the object
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* @param name name of the object
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* @param a base address of the write
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* @param a base address of the write
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* @param mmu the memory controller
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* @param mmu the memory controller
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* @param hier object to store parameters universal the device hierarchy
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* @param bus The bus that this device is attached to
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* @param devicename device that is not implemented
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* @param devicename device that is not implemented
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*/
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*/
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BadDevice(const std::string &name, Addr a, MemoryController *mmu,
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BadDevice(const std::string &name, Addr a, MemoryController *mmu,
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const std::string &devicename);
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HierParams *hier, Bus *bus, const std::string &devicename);
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/**
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/**
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* On a read event we just panic aand hopefully print a
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* On a read event we just panic aand hopefully print a
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*/
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/** @todo add serialize/unserialize */
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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};
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#endif // __BADDEV_HH__
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#endif // __BADDEV_HH__
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@ -668,7 +668,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
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Param<uint32_t> pci_bus;
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Param<uint32_t> pci_bus;
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Param<uint32_t> pci_dev;
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Param<uint32_t> pci_dev;
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Param<uint32_t> pci_func;
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Param<uint32_t> pci_func;
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SimObjectParam<Bus *> host_bus;
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SimObjectParam<Bus *> io_bus;
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SimObjectParam<HierParams *> hier;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
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END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
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@ -684,7 +684,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
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INIT_PARAM(pci_bus, "PCI bus ID"),
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INIT_PARAM(pci_bus, "PCI bus ID"),
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INIT_PARAM(pci_dev, "PCI device number"),
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INIT_PARAM(pci_dev, "PCI device number"),
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INIT_PARAM(pci_func, "PCI function code"),
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INIT_PARAM(pci_func, "PCI function code"),
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INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
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INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(IdeController)
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END_INIT_SIM_OBJECT_PARAMS(IdeController)
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@ -693,7 +693,7 @@ CREATE_SIM_OBJECT(IdeController)
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{
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{
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return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
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return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
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configspace, configdata, tsunami, pci_bus,
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configspace, configdata, tsunami, pci_bus,
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pci_dev, pci_func, host_bus, hier);
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pci_dev, pci_func, io_bus, hier);
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}
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}
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REGISTER_SIM_OBJECT("IdeController", IdeController)
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REGISTER_SIM_OBJECT("IdeController", IdeController)
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@ -198,12 +198,6 @@ class IdeController : public PciDev
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*/
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Cache access timing specific to device
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* @param req Memory request
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*/
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Tick cacheAccess(MemReqPtr &req);
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/**
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/**
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* Serialize this object to the given output stream.
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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* @param os The stream to serialize to.
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@ -217,5 +211,11 @@ class IdeController : public PciDev
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*/
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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};
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#endif // __IDE_CTRL_HH_
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#endif // __IDE_CTRL_HH_
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@ -131,8 +131,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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pioInterface = newPioInterface(name, hier, payload_bus, this,
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pioInterface = newPioInterface(name, hier, payload_bus, this,
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&NSGigE::cacheAccess);
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&NSGigE::cacheAccess);
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dmaInterface = new DMAInterface<Bus>(name + ".dma",
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dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus,
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payload_bus, payload_bus, 1);
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payload_bus, 1);
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}
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}
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@ -244,12 +244,22 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
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switch (offset) {
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0) {
|
if (BARAddrs[0] != 0) {
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addr = BARAddrs[0];
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if (pioInterface)
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if (pioInterface)
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pioInterface->addAddrRange(addr, addr + size - 1);
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pioInterface->addAddrRange(BARAddrs[0], BARAddrs[0] + BARSize[0] - 1);
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BARAddrs[0] &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR1:
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if (BARAddrs[1] != 0) {
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|
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if (pioInterface)
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pioInterface->addAddrRange(BARAddrs[1], BARAddrs[1] + BARSize[1] - 1);
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BARAddrs[1] &= PA_UNCACHED_MASK;
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addr &= PA_UNCACHED_MASK;
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|
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}
|
}
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break;
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break;
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}
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}
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|
|
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@ -35,22 +35,29 @@
|
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#include <vector>
|
#include <vector>
|
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|
|
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#include "base/trace.hh"
|
#include "base/trace.hh"
|
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#include "cpu/exec_context.hh"
|
|
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#include "dev/scsi_ctrl.hh"
|
|
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#include "dev/pciconfigall.hh"
|
#include "dev/pciconfigall.hh"
|
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#include "dev/pcidev.hh"
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#include "dev/pcidev.hh"
|
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#include "mem/bus/bus.hh"
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|
#include "mem/bus/pio_interface.hh"
|
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|
#include "mem/bus/pio_interface_impl.hh"
|
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#include "mem/functional_mem/memory_control.hh"
|
#include "mem/functional_mem/memory_control.hh"
|
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#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
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#include "sim/system.hh"
|
#include "sim/system.hh"
|
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|
|
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using namespace std;
|
using namespace std;
|
||||||
|
|
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PciConfigAll::PciConfigAll(const string &name, Addr a,
|
PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
|
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MemoryController *mmu)
|
HierParams *hier, Bus *bus)
|
||||||
: FunctionalMemory(name), addr(a)
|
: PioDevice(name), addr(a)
|
||||||
{
|
{
|
||||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
|
if (bus) {
|
||||||
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
|
&PciConfigAll::cacheAccess);
|
||||||
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
|
}
|
||||||
|
|
||||||
// Make all the pointers to devices null
|
// Make all the pointers to devices null
|
||||||
for(int x=0; x < MAX_PCI_DEV; x++)
|
for(int x=0; x < MAX_PCI_DEV; x++)
|
||||||
for(int y=0; y < MAX_PCI_FUNC; y++)
|
for(int y=0; y < MAX_PCI_FUNC; y++)
|
||||||
|
@ -165,6 +172,12 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
*/
|
*/
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
PciConfigAll::cacheAccess(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return curTick + 1000;
|
||||||
|
}
|
||||||
|
|
||||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||||
|
@ -172,6 +185,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
Param<Addr> mask;
|
Param<Addr> mask;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||||
|
|
||||||
|
@ -179,13 +194,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||||
|
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address"),
|
||||||
INIT_PARAM(mask, "Address Mask")
|
INIT_PARAM(mask, "Address Mask"),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
|
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(PciConfigAll)
|
CREATE_SIM_OBJECT(PciConfigAll)
|
||||||
{
|
{
|
||||||
return new PciConfigAll(getInstanceName(), addr, mmu);
|
return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
|
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
|
||||||
|
|
|
@ -34,8 +34,10 @@
|
||||||
#ifndef __PCICONFIGALL_HH__
|
#ifndef __PCICONFIGALL_HH__
|
||||||
#define __PCICONFIGALL_HH__
|
#define __PCICONFIGALL_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/functional_memory.hh"
|
|
||||||
#include "dev/pcireg.h"
|
#include "dev/pcireg.h"
|
||||||
|
#include "base/range.hh"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
|
|
||||||
static const uint32_t MAX_PCI_DEV = 32;
|
static const uint32_t MAX_PCI_DEV = 32;
|
||||||
static const uint32_t MAX_PCI_FUNC = 8;
|
static const uint32_t MAX_PCI_FUNC = 8;
|
||||||
|
@ -49,7 +51,7 @@ class PciDev;
|
||||||
* space and passes the requests on to TsunamiPCIDev devices as
|
* space and passes the requests on to TsunamiPCIDev devices as
|
||||||
* appropriate.
|
* appropriate.
|
||||||
*/
|
*/
|
||||||
class PciConfigAll : public FunctionalMemory
|
class PciConfigAll : public PioDevice
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
Addr addr;
|
Addr addr;
|
||||||
|
@ -67,8 +69,11 @@ class PciConfigAll : public FunctionalMemory
|
||||||
* @param name name of the object
|
* @param name name of the object
|
||||||
* @param a base address of the write
|
* @param a base address of the write
|
||||||
* @param mmu the memory controller
|
* @param mmu the memory controller
|
||||||
|
* @param hier object to store parameters universal the device hierarchy
|
||||||
|
* @param bus The bus that this device is attached to
|
||||||
*/
|
*/
|
||||||
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu);
|
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
|
||||||
|
HierParams *hier, Bus *bus);
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -123,6 +128,12 @@ class PciConfigAll : public FunctionalMemory
|
||||||
*/
|
*/
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return how long this access will take.
|
||||||
|
* @param req the memory request to calcuate
|
||||||
|
* @return Tick when the request is done
|
||||||
|
*/
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __PCICONFIGALL_HH__
|
#endif // __PCICONFIGALL_HH__
|
||||||
|
|
|
@ -35,21 +35,23 @@
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/exec_context.hh"
|
|
||||||
#include "dev/console.hh"
|
#include "dev/console.hh"
|
||||||
#include "dev/tsunami_cchip.hh"
|
#include "dev/tsunami_cchip.hh"
|
||||||
#include "dev/tsunamireg.h"
|
#include "dev/tsunamireg.h"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
#include "cpu/intr_control.hh"
|
#include "mem/bus/bus.hh"
|
||||||
|
#include "mem/bus/pio_interface.hh"
|
||||||
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
#include "mem/functional_mem/memory_control.hh"
|
#include "mem/functional_mem/memory_control.hh"
|
||||||
|
#include "cpu/intr_control.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
|
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
|
||||||
MemoryController *mmu)
|
MemoryController *mmu, HierParams *hier, Bus* bus)
|
||||||
: FunctionalMemory(name), addr(a), tsunami(t)
|
: PioDevice(name), addr(a), tsunami(t)
|
||||||
{
|
{
|
||||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
|
@ -61,6 +63,12 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
|
||||||
RTCInterrupting[i] = false;
|
RTCInterrupting[i] = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (bus) {
|
||||||
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
|
&TsunamiCChip::cacheAccess);
|
||||||
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
|
}
|
||||||
|
|
||||||
drir = 0;
|
drir = 0;
|
||||||
misc = 0;
|
misc = 0;
|
||||||
|
|
||||||
|
@ -373,6 +381,13 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
|
||||||
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
TsunamiCChip::cacheAccess(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return curTick + 1000;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void
|
void
|
||||||
TsunamiCChip::serialize(std::ostream &os)
|
TsunamiCChip::serialize(std::ostream &os)
|
||||||
{
|
{
|
||||||
|
@ -402,6 +417,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
SimObjectParam<Tsunami *> tsunami;
|
SimObjectParam<Tsunami *> tsunami;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
|
@ -409,13 +426,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
INIT_PARAM(tsunami, "Tsunami"),
|
INIT_PARAM(tsunami, "Tsunami"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address")
|
INIT_PARAM(addr, "Device Address"),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiCChip)
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
||||||
{
|
{
|
||||||
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu);
|
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|
||||||
|
|
|
@ -33,13 +33,14 @@
|
||||||
#ifndef __TSUNAMI_CCHIP_HH__
|
#ifndef __TSUNAMI_CCHIP_HH__
|
||||||
#define __TSUNAMI_CCHIP_HH__
|
#define __TSUNAMI_CCHIP_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/functional_memory.hh"
|
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
#include "base/range.hh"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami CChip
|
* Tsunami CChip
|
||||||
*/
|
*/
|
||||||
class TsunamiCChip : public FunctionalMemory
|
class TsunamiCChip : public PioDevice
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
/** The base address of this device */
|
/** The base address of this device */
|
||||||
|
@ -95,9 +96,11 @@ class TsunamiCChip : public FunctionalMemory
|
||||||
* @param t pointer back to the Tsunami object that we belong to.
|
* @param t pointer back to the Tsunami object that we belong to.
|
||||||
* @param a address we are mapped at.
|
* @param a address we are mapped at.
|
||||||
* @param mmu pointer to the memory controller that sends us events.
|
* @param mmu pointer to the memory controller that sends us events.
|
||||||
|
* @param hier object to store parameters universal the device hierarchy
|
||||||
|
* @param bus The bus that this device is attached to
|
||||||
*/
|
*/
|
||||||
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
|
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
|
||||||
MemoryController *mmu);
|
MemoryController *mmu, HierParams *hier, Bus *bus);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Process a read to the CChip.
|
* Process a read to the CChip.
|
||||||
|
@ -145,6 +148,13 @@ class TsunamiCChip : public FunctionalMemory
|
||||||
* @param section The section name of this object
|
* @param section The section name of this object
|
||||||
*/
|
*/
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return how long this access will take.
|
||||||
|
* @param req the memory request to calcuate
|
||||||
|
* @return Tick when the request is done
|
||||||
|
*/
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_CCHIP_HH__
|
#endif // __TSUNAMI_CCHIP_HH__
|
||||||
|
|
|
@ -37,15 +37,16 @@
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/exec_context.hh"
|
|
||||||
#include "dev/console.hh"
|
#include "dev/console.hh"
|
||||||
#include "dev/tlaser_clock.hh"
|
|
||||||
#include "dev/tsunami_io.hh"
|
#include "dev/tsunami_io.hh"
|
||||||
#include "dev/tsunamireg.h"
|
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
#include "mem/functional_mem/memory_control.hh"
|
#include "mem/bus/bus.hh"
|
||||||
|
#include "mem/bus/pio_interface.hh"
|
||||||
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "dev/tsunami_cchip.hh"
|
#include "dev/tsunami_cchip.hh"
|
||||||
|
#include "dev/tsunamireg.h"
|
||||||
|
#include "mem/functional_mem/memory_control.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
|
@ -122,11 +123,17 @@ TsunamiIO::ClockEvent::Status()
|
||||||
}
|
}
|
||||||
|
|
||||||
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
|
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
|
||||||
Addr a, MemoryController *mmu)
|
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus)
|
||||||
: FunctionalMemory(name), addr(a), tsunami(t), rtc(t)
|
: PioDevice(name), addr(a), tsunami(t), rtc(t)
|
||||||
{
|
{
|
||||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
|
if (bus) {
|
||||||
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
|
&TsunamiIO::cacheAccess);
|
||||||
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
|
}
|
||||||
|
|
||||||
// set the back pointer from tsunami to myself
|
// set the back pointer from tsunami to myself
|
||||||
tsunami->io = this;
|
tsunami->io = this;
|
||||||
|
|
||||||
|
@ -375,6 +382,12 @@ TsunamiIO::clearPIC(uint8_t bitvector)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
TsunamiIO::cacheAccess(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return curTick + 1000;
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
TsunamiIO::serialize(std::ostream &os)
|
TsunamiIO::serialize(std::ostream &os)
|
||||||
{
|
{
|
||||||
|
@ -425,6 +438,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
Param<time_t> time;
|
Param<time_t> time;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
|
|
||||||
|
@ -434,13 +449,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
INIT_PARAM_DFLT(time, "System time to use "
|
INIT_PARAM_DFLT(time, "System time to use "
|
||||||
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
|
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address")
|
INIT_PARAM(addr, "Device Address"),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiIO)
|
CREATE_SIM_OBJECT(TsunamiIO)
|
||||||
{
|
{
|
||||||
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu);
|
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
|
||||||
|
io_bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|
||||||
|
|
|
@ -33,7 +33,8 @@
|
||||||
#ifndef __TSUNAMI_DMA_HH__
|
#ifndef __TSUNAMI_DMA_HH__
|
||||||
#define __TSUNAMI_DMA_HH__
|
#define __TSUNAMI_DMA_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/functional_memory.hh"
|
#include "dev/io_device.hh"
|
||||||
|
#include "base/range.hh"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
|
||||||
/** How often the RTC interrupts */
|
/** How often the RTC interrupts */
|
||||||
|
@ -43,7 +44,7 @@ static const int RTC_RATE = 1024;
|
||||||
* Tsunami I/O device is a catch all for all the south bridge stuff we care
|
* Tsunami I/O device is a catch all for all the south bridge stuff we care
|
||||||
* to implement.
|
* to implement.
|
||||||
*/
|
*/
|
||||||
class TsunamiIO : public FunctionalMemory
|
class TsunamiIO : public PioDevice
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
/** The base address of this device */
|
/** The base address of this device */
|
||||||
|
@ -134,6 +135,7 @@ class TsunamiIO : public FunctionalMemory
|
||||||
* @return a description
|
* @return a description
|
||||||
*/
|
*/
|
||||||
virtual const char *description();
|
virtual const char *description();
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/** uip UpdateInProgess says that the rtc is updating, but we just fake it
|
/** uip UpdateInProgess says that the rtc is updating, but we just fake it
|
||||||
|
@ -208,7 +210,7 @@ class TsunamiIO : public FunctionalMemory
|
||||||
* @param mmu pointer to the memory controller that sends us events.
|
* @param mmu pointer to the memory controller that sends us events.
|
||||||
*/
|
*/
|
||||||
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
|
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
|
||||||
Addr a, MemoryController *mmu);
|
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Create the tm struct from seconds since 1970
|
* Create the tm struct from seconds since 1970
|
||||||
|
@ -256,6 +258,9 @@ class TsunamiIO : public FunctionalMemory
|
||||||
* @param section The section name of this object
|
* @param section The section name of this object
|
||||||
*/
|
*/
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_IO_HH__
|
#endif // __TSUNAMI_IO_HH__
|
||||||
|
|
|
@ -35,14 +35,12 @@
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/exec_context.hh"
|
|
||||||
#include "dev/console.hh"
|
|
||||||
#include "dev/etherdev.hh"
|
|
||||||
#include "dev/scsi_ctrl.hh"
|
|
||||||
#include "dev/tlaser_clock.hh"
|
|
||||||
#include "dev/tsunami_pchip.hh"
|
#include "dev/tsunami_pchip.hh"
|
||||||
#include "dev/tsunamireg.h"
|
#include "dev/tsunamireg.h"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
#include "mem/bus/bus.hh"
|
||||||
|
#include "mem/bus/pio_interface.hh"
|
||||||
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
#include "mem/functional_mem/memory_control.hh"
|
#include "mem/functional_mem/memory_control.hh"
|
||||||
#include "mem/functional_mem/physical_memory.hh"
|
#include "mem/functional_mem/physical_memory.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
|
@ -51,8 +49,9 @@
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
|
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
|
||||||
MemoryController *mmu)
|
MemoryController *mmu, HierParams *hier,
|
||||||
: FunctionalMemory(name), addr(a), tsunami(t)
|
Bus *bus)
|
||||||
|
: PioDevice(name), addr(a), tsunami(t)
|
||||||
{
|
{
|
||||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
|
@ -62,6 +61,13 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
|
||||||
tba[i] = 0;
|
tba[i] = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (bus) {
|
||||||
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
|
&TsunamiPChip::cacheAccess);
|
||||||
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
// initialize pchip control register
|
// initialize pchip control register
|
||||||
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
|
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
|
||||||
|
|
||||||
|
@ -342,11 +348,19 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
UNSERIALIZE_ARRAY(tba, 4);
|
UNSERIALIZE_ARRAY(tba, 4);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
TsunamiPChip::cacheAccess(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return curTick + 1000;
|
||||||
|
}
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
SimObjectParam<Tsunami *> tsunami;
|
SimObjectParam<Tsunami *> tsunami;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
|
@ -354,13 +368,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
INIT_PARAM(tsunami, "Tsunami"),
|
INIT_PARAM(tsunami, "Tsunami"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address")
|
INIT_PARAM(addr, "Device Address"),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiPChip)
|
CREATE_SIM_OBJECT(TsunamiPChip)
|
||||||
{
|
{
|
||||||
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
|
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
|
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
|
||||||
|
|
|
@ -33,13 +33,14 @@
|
||||||
#ifndef __TSUNAMI_PCHIP_HH__
|
#ifndef __TSUNAMI_PCHIP_HH__
|
||||||
#define __TSUNAMI_PCHIP_HH__
|
#define __TSUNAMI_PCHIP_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/functional_memory.hh"
|
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
#include "base/range.hh"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami PChip
|
* Tsunami PChip
|
||||||
*/
|
*/
|
||||||
class TsunamiPChip : public FunctionalMemory
|
class TsunamiPChip : public PioDevice
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
/** The base address of this device */
|
/** The base address of this device */
|
||||||
|
@ -75,9 +76,11 @@ class TsunamiPChip : public FunctionalMemory
|
||||||
* @param t a pointer to the tsunami device
|
* @param t a pointer to the tsunami device
|
||||||
* @param a the address which we respond to
|
* @param a the address which we respond to
|
||||||
* @param mmu the mmu we are to register with
|
* @param mmu the mmu we are to register with
|
||||||
|
* @param hier object to store parameters universal the device hierarchy
|
||||||
|
* @param bus The bus that this device is attached to
|
||||||
*/
|
*/
|
||||||
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
|
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
|
||||||
MemoryController *mmu);
|
MemoryController *mmu, HierParams *hier, Bus *bus);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Translate a PCI bus address to a memory address for DMA.
|
* Translate a PCI bus address to a memory address for DMA.
|
||||||
|
@ -115,6 +118,13 @@ class TsunamiPChip : public FunctionalMemory
|
||||||
* @param section The section name of this object
|
* @param section The section name of this object
|
||||||
*/
|
*/
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return how long this access will take.
|
||||||
|
* @param req the memory request to calcuate
|
||||||
|
* @return Tick when the request is done
|
||||||
|
*/
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_PCHIP_HH__
|
#endif // __TSUNAMI_PCHIP_HH__
|
||||||
|
|
|
@ -82,7 +82,7 @@ TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
|
||||||
if (bus) {
|
if (bus) {
|
||||||
pioInterface = newPioInterface(name, hier, bus, this,
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
&TsunamiUart::cacheAccess);
|
&TsunamiUart::cacheAccess);
|
||||||
pioInterface->addAddrRange(addr, addr + size - 1);
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
IER = 0;
|
IER = 0;
|
||||||
|
|
|
@ -80,7 +80,11 @@ class TsunamiUart : public PioDevice
|
||||||
virtual void serialize(std::ostream &os);
|
virtual void serialize(std::ostream &os);
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
public:
|
/**
|
||||||
|
* Return how long this access will take.
|
||||||
|
* @param req the memory request to calcuate
|
||||||
|
* @return Tick when the request is done
|
||||||
|
*/
|
||||||
Tick cacheAccess(MemReqPtr &req);
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -132,10 +132,11 @@
|
||||||
#define RTC_CONTROL_REGISTERD 13 // control register D
|
#define RTC_CONTROL_REGISTERD 13 // control register D
|
||||||
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
|
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
|
||||||
|
|
||||||
#define PCHIP_PCI0_MEMORY ULL(0x10000000000)
|
#define PCHIP_PCI0_MEMORY ULL(0x00000000000)
|
||||||
#define PCHIP_PCI0_IO ULL(0x101FC000000)
|
#define PCHIP_PCI0_IO ULL(0x001FC000000)
|
||||||
#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
|
#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
|
||||||
#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
|
#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
|
||||||
|
#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
|
||||||
|
|
||||||
|
|
||||||
// UART Defines
|
// UART Defines
|
||||||
|
|
Loading…
Reference in a new issue