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Move some common full-system CPU initialization from the

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SimpleCPU & FullCPU constructors to AlphaISA::initCPU().

cpu/simple_cpu/simple_cpu.cc:
    Move some common full-system CPU initialization from the
    SimpleCPU & FullCPU constructors to AlphaISA::initCPU().
    Make 'fault' local to SimpleCPU::tick.
cpu/simple_cpu/simple_cpu.hh:
    Make 'fault' local to SimpleCPU::tick (not an object member).

--HG--
extra : convert_revision : e878dedfff06aac0548aca8b14d66c18b8916895
This commit is contained in:
Steve Reinhardt 2003-10-24 23:20:27 -07:00
parent 91cb532f9f
commit 02d80c96b7
3 changed files with 10 additions and 14 deletions
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6
arch/alpha/ev5.cc
View file

@ -47,6 +47,11 @@ void
AlphaISA::initCPU(RegFile *regs) AlphaISA::initCPU(RegFile *regs)
{ {
initIPRs(regs); initIPRs(regs);
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
regs->npc = regs->pc + sizeof(MachInst);
} }
void void
@ -97,6 +102,7 @@ AlphaISA::initIPRs(RegFile *regs)
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
ipr[IPR_PAL_BASE] = PAL_BASE; ipr[IPR_PAL_BASE] = PAL_BASE;
ipr[IPR_MCSR] = 0x6;
} }

15
cpu/simple_cpu/simple_cpu.cc
View file

@ -126,19 +126,10 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
xc = new ExecContext(this, 0, system, itb, dtb, mem); xc = new ExecContext(this, 0, system, itb, dtb, mem);
// initialize CPU, including PC
TheISA::initCPU(&xc->regs); TheISA::initCPU(&xc->regs);
IntReg *ipr = xc->regs.ipr;
ipr[TheISA::IPR_MCSR] = 0x6;
AlphaISA::swap_palshadow(&xc->regs, true);
fault = Reset_Fault;
xc->regs.pc = ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
xc->regs.npc = xc->regs.pc + sizeof(MachInst);
#else #else
xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0); xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
fault = No_Fault;
#endif // !FULL_SYSTEM #endif // !FULL_SYSTEM
icacheInterface = icache_interface; icacheInterface = icache_interface;
@ -524,8 +515,10 @@ SimpleCPU::tick()
{ {
traceData = NULL; traceData = NULL;
Fault fault = No_Fault;
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
if (fault == No_Fault && AlphaISA::check_interrupts && if (AlphaISA::check_interrupts &&
xc->cpu->check_interrupts() && xc->cpu->check_interrupts() &&
!PC_PAL(xc->regs.pc) && !PC_PAL(xc->regs.pc) &&
status() != IcacheMissComplete) { status() != IcacheMissComplete) {

3
cpu/simple_cpu/simple_cpu.hh
View file

@ -154,9 +154,6 @@ class SimpleCPU : public BaseCPU
// current instruction // current instruction
MachInst inst; MachInst inst;
// current fault status
Fault fault;
// Refcounted pointer to the one memory request. // Refcounted pointer to the one memory request.
MemReqPtr memReq; MemReqPtr memReq;