Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
This commit is contained in:
commit
01c959aeaf
8 changed files with 111 additions and 39 deletions
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@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown()
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//ASI_LDTX_N_L
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0x2F: TwinLoad::ldtx_n_l(
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{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
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//ASI_LDTX_P
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0xE2: TwinLoad::ldtx_p(
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{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
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default: ldtwa({{
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uint64_t val = Mem.udw;
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RdLow = val<31:0>;
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@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@ -451,6 +451,8 @@ let {{
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flag_code = ''
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if (microPc == 7):
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flag_code = "flags[IsLastMicroOp] = true;"
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elif (microPc == 0):
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flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
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else:
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flag_code = "flags[IsDelayedCommit] = true;"
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pcedCode = matcher.sub("Frd_%d" % microPc, code)
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@ -492,7 +494,7 @@ let {{
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flag_code = "flags[IsLastMicroOp] = true;"
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pcedCode = matcher.sub("RdHigh", code)
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else:
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flag_code = "flags[IsDelayedCommit] = true;"
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flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
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pcedCode = matcher.sub("RdLow", code)
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iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
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opt_flags, {"ea_code": addrCalcReg,
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@ -81,21 +81,44 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
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MapIter i;
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TlbEntry *new_entry = NULL;
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TlbRange tr;
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// TlbRange tr;
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int x;
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cacheValid = false;
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tr.va = va;
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/* tr.va = va;
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tr.size = PTE.size() - 1;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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*/
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DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
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va, PTE.paddr(), partition_id, context_id, (int)real, entry);
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// Demap any entry that conflicts
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for (x = 0; x < size; x++) {
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if (tlb[x].range.real == real &&
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tlb[x].range.partitionId == partition_id &&
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tlb[x].range.va < va + PTE.size() - 1 &&
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tlb[x].range.va + tlb[x].range.size >= va &&
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(real || tlb[x].range.contextId == context_id ))
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{
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if (tlb[x].valid) {
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freeList.push_front(&tlb[x]);
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DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
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tlb[x].valid = false;
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if (tlb[x].used) {
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tlb[x].used = false;
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usedEntries--;
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}
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lookupTable.erase(tlb[x].range);
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}
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}
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}
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/*
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i = lookupTable.find(tr);
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if (i != lookupTable.end()) {
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i->second->valid = false;
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@ -108,7 +131,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
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i->second);
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lookupTable.erase(i);
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}
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*/
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if (entry != -1) {
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assert(entry < size && entry >= 0);
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@ -127,7 +150,6 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
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} while (tlb[x].pte.locked());
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lastReplaced = x;
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new_entry = &tlb[x];
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lookupTable.erase(new_entry->range);
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}
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/*
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for (x = 0; x < size; x++) {
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@ -142,10 +164,15 @@ insertAllLocked:
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// Update the last ently if their all locked
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if (!new_entry) {
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new_entry = &tlb[size-1];
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lookupTable.erase(new_entry->range);
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}
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freeList.remove(new_entry);
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if (new_entry->valid && new_entry->used)
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usedEntries--;
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lookupTable.erase(new_entry->range);
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DPRINTF(TLB, "Using entry: %#X\n", new_entry);
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assert(PTE.valid());
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@ -315,10 +342,12 @@ TLB::invalidateAll()
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cacheValid = false;
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freeList.clear();
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lookupTable.clear();
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for (x = 0; x < size; x++) {
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if (tlb[x].valid == true)
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freeList.push_back(&tlb[x]);
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tlb[x].valid = false;
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tlb[x].used = false;
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}
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usedEntries = 0;
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}
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@ -625,13 +654,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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return new DataAccessException;
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}
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} /*else if (hpriv) {*/
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if (asi == ASI_P) {
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}
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if (asi == ASI_P || asi == ASI_LDTX_P) {
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ct = Primary;
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context = pri_context;
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goto continueDtbFlow;
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}
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//}
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if (!implicit) {
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if (AsiIsLittle(asi))
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@ -640,10 +668,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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panic("Block ASIs not supported\n");
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if (AsiIsNoFault(asi))
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panic("No Fault ASIs not supported\n");
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if (write && asi == ASI_LDTX_P)
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// block init store (like write hint64)
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goto continueDtbFlow;
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if (!write && asi == ASI_QUAD_LDD)
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if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
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goto continueDtbFlow;
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if (AsiIsTwin(asi))
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@ -880,6 +905,9 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
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pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
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break;
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case 0x18:
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
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break;
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case 0x30:
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
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break;
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@ -893,6 +921,12 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
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pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
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break;
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case 0x18:
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
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break;
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case 0x20:
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
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break;
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case 0x30:
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
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break;
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@ -1074,6 +1108,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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break;
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case ASI_IMMU:
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switch (va) {
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case 0x18:
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tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
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break;
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case 0x30:
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tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
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break;
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@ -1145,6 +1182,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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break;
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case ASI_DMMU:
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switch (va) {
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case 0x18:
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tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
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break;
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case 0x30:
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tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
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break;
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@ -63,19 +63,19 @@ RawObject::RawObject(const std::string &_filename, int _fd, size_t _len,
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bool
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RawObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask)
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{
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int fnameStart = filename.rfind('/',filename.size()) + 1;
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/* int fnameStart = filename.rfind('/',filename.size()) + 1;
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int extStart = filename.rfind('.',filename.size());
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symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart,
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extStart-fnameStart) + "_start");
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extStart-fnameStart) + "_start");*/
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return true;
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}
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bool
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RawObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask)
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{
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int fnameStart = filename.rfind('/',filename.size()) + 1;
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/* int fnameStart = filename.rfind('/',filename.size()) + 1;
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int extStart = filename.rfind('.',filename.size());
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symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart,
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extStart-fnameStart) + "_start");
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extStart-fnameStart) + "_start");*/
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return true;
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}
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@ -59,6 +59,7 @@ using namespace TheISA;
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#if THE_ISA == SPARC_ISA && FULL_SYSTEM
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static int diffcount = 0;
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static bool wasMicro = false;
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#endif
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namespace Trace {
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@ -124,6 +125,7 @@ inline void printLevelHeader(ostream & os, int level)
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void
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Trace::InstRecord::dump(ostream &outs)
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{
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DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
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if (flags[PRINT_REG_DELTA])
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{
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#if THE_ISA == SPARC_ISA
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@ -315,6 +317,24 @@ Trace::InstRecord::dump(ostream &outs)
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bool diffTlb = false;
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Addr m5Pc, lgnPc;
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// We took a trap on a micro-op...
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if (wasMicro && !staticInst->isMicroOp())
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{
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// let's skip comparing this cycle
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while (!compared)
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if (shared_data->flags == OWN_M5) {
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shared_data->flags = OWN_LEGION;
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compared = true;
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}
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compared = false;
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wasMicro = false;
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}
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if (staticInst->isLastMicroOp())
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wasMicro = false;
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else if (staticInst->isMicroOp())
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wasMicro = true;
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
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while (!compared) {
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@ -587,24 +607,28 @@ Trace::InstRecord::dump(ostream &outs)
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<< endl;*/
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}
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}
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if (diffTlb) {
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printColumnLabels(outs);
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char label[8];
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for (int x = 0; x < 64; x++) {
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if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
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thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
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sprintf(label, "I-TLB:%02d", x);
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printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]);
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printRegPair(outs, label, thread->getITBPtr()->TteRead(x),
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shared_data->itb[x]);
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}
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}
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for (int x = 0; x < 64; x++) {
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if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
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thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
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sprintf(label, "D-TLB:%02d", x);
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printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]);
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printRegPair(outs, label, thread->getDTBPtr()->TteRead(x),
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shared_data->dtb[x]);
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}
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}
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thread->getITBPtr()->dumpAll();
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thread->getDTBPtr()->dumpAll();
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}
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diffcount++;
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if (diffcount > 2)
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@ -497,7 +497,7 @@ AtomicSimpleCPU::tick()
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// @todo remove me after debugging with legion done
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if (curStaticInst && (!curStaticInst->isMicroOp() ||
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curStaticInst->isLastMicroOp()))
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curStaticInst->isFirstMicroOp()))
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instCnt++;
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if (simulate_stalls) {
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@ -437,6 +437,7 @@ void
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BaseSimpleCPU::advancePC(Fault fault)
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{
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if (fault != NoFault) {
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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fault->invoke(tc);
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} else {
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//If we're at the last micro op for this instruction
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@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted
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IsMicroOp, ///< Is a microop
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IsDelayedCommit, ///< This microop doesn't commit right away
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IsLastMicroOp, ///< This microop ends a microop sequence
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IsFirstMicroOp, ///< This microop begins a microop sequence
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//This flag doesn't do anything yet
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IsMicroBranch, ///< This microop branches within the microcode for a macroop
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@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted
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bool isMicroOp() const { return flags[IsMicroOp]; }
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bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
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bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
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bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
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//This flag doesn't do anything yet
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bool isMicroBranch() const { return flags[IsMicroBranch]; }
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//@}
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