Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

configs/common/CacheConfig.py

@@ -52,8 +52,8 @@ def config_cache(options, system):
                 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                       L1Cache(size = '64kB'))
         if options.l2cache:
-            system.cpu[i].connectMemPorts(system.tol2bus)
+            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
         else:
-            system.cpu[i].connectMemPorts(system.membus)
+            system.cpu[i].connectAllPorts(system.membus)
 
     return system

configs/example/fs.py

@@ -178,7 +178,7 @@ if len(bm) == 2:
     elif buildEnv['TARGET_ISA'] == 'arm':
         drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
-    drive_sys.cpu.connectMemPorts(drive_sys.membus)
+    drive_sys.cpu.connectAllPorts(drive_sys.membus)
     if options.fastmem:
         drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:

configs/splash2/run.py

@@ -218,7 +218,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
                                 L1(size = options.l1size, assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2bus)
+    cpu.connectAllPorts(system.toL2bus, system.membus)
 
 
 # ----------------------

src/cpu/BaseCPU.py

@@ -150,48 +150,53 @@ class BaseCPU(MemObject):
 
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
-    _mem_ports = []
+    _cached_ports = []
+    if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+        _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+    _uncached_ports = []
     if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
-        _mem_ports = ["itb.walker.port",
+        _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
-                      "dtb.walker.port",
-                      "interrupts.pio",
-                      "interrupts.int_port"]
 
-    if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
+    def connectCachedPorts(self, bus):
-        _mem_ports = ["itb.walker.port",
+        for p in self._cached_ports:
-                      "dtb.walker.port"]
+            exec('self.%s = bus.port' % p)
 
-    def connectMemPorts(self, bus):
+    def connectUncachedPorts(self, bus):
-        for p in self._mem_ports:
+        for p in self._uncached_ports:
-            if p != 'physmem_port':
+            exec('self.%s = bus.port' % p)
-                exec('self.%s = bus.port' % p)
+
+    def connectAllPorts(self, cached_bus, uncached_bus = None):
+        self.connectCachedPorts(cached_bus)
+        if not uncached_bus:
+            uncached_bus = cached_bus
+        self.connectUncachedPorts(uncached_bus)
 
     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
-        assert(len(self._mem_ports) < 8)
+        assert(len(self._cached_ports) < 7)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
-        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
             if buildEnv['TARGET_ISA'] == 'x86':
                 self.itb_walker_cache = iwc
                 self.dtb_walker_cache = dwc
                 self.itb.walker.port = iwc.cpu_side
                 self.dtb.walker.port = dwc.cpu_side
-                self._mem_ports += ["itb_walker_cache.mem_side", \
+                self._cached_ports += ["itb_walker_cache.mem_side", \
-                                    "dtb_walker_cache.mem_side"]
+                                       "dtb_walker_cache.mem_side"]
-                self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
             elif buildEnv['TARGET_ISA'] == 'arm':
-                self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
         self.toL2Bus = Bus()
-        self.connectMemPorts(self.toL2Bus)
+        self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.l2cache.cpu_side = self.toL2Bus.port
-        self._mem_ports = ['l2cache.mem_side']
+        self._cached_ports = ['l2cache.mem_side']
 
     if buildEnv['TARGET_ISA'] == 'mips':
         CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")

src/cpu/inorder/InOrderCPU.py

@@ -46,7 +46,7 @@ class InOrderCPU(BaseCPU):
     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    _cached_ports = ['icache_port', 'dcache_port']
 
     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")

src/cpu/o3/O3CPU.py

@@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU):
     cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
 
     decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")

src/cpu/simple/AtomicSimpleCPU.py

@@ -37,5 +37,5 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + \
+    _cached_ports = BaseSimpleCPU._cached_ports + \
-                    ['icache_port', 'dcache_port', 'physmem_port']
+                    ['icache_port', 'dcache_port']

src/cpu/simple/TimingSimpleCPU.py

@@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']

tests/configs/inorder-timing.py

@@ -47,6 +47,6 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

tests/configs/o3-timing-mp-ruby.py

@@ -40,7 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
+    cpu.connectAllPorts(system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

tests/configs/o3-timing-mp.py

@@ -72,7 +72,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

tests/configs/o3-timing-ruby.py

@@ -41,6 +41,6 @@ system = System(cpu = cpu,
                 physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

tests/configs/o3-timing.py

@@ -46,6 +46,6 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

tests/configs/realview-simple-atomic.py

@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/realview-simple-timing.py

@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/simple-atomic-mp-ruby.py

@@ -41,7 +41,7 @@ system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 # add L1 caches
 for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
+    cpu.connectAllPorts(system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

tests/configs/simple-atomic-mp.py

@@ -71,7 +71,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

tests/configs/simple-atomic.py

@@ -33,7 +33,7 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
+system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
 root = Root(system = system)

tests/configs/simple-timing-mp.py

@@ -71,7 +71,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

tests/configs/simple-timing.py

@@ -43,7 +43,7 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system = system)

tests/configs/t1000-simple-atomic.py

@@ -34,7 +34,7 @@ import FSConfig
 cpu = AtomicSimpleCPU(cpu_id=0)
 system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system=system)
 

tests/configs/tsunami-o3-dual.py

@@ -92,7 +92,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/tsunami-o3.py

@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/tsunami-simple-atomic-dual.py

@@ -90,7 +90,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/tsunami-simple-atomic.py

@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/tsunami-simple-timing-dual.py

@@ -90,7 +90,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/tsunami-simple-timing.py

@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

tests/configs/twosys-tsunami-simple-atomic.py

@@ -35,12 +35,12 @@ from Benchmarks import *
 test_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-stream-client.rcS'))
 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-test_sys.cpu.connectMemPorts(test_sys.membus)
+test_sys.cpu.connectAllPorts(test_sys.membus)
 
 drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-drive_sys.cpu.connectMemPorts(drive_sys.membus)
+drive_sys.cpu.connectAllPorts(drive_sys.membus)
 
 root = makeDualRoot(test_sys, drive_sys, "ethertrace")