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Ruby: Fix instantiations of DMA controller and sequencer

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The patch on Ruby functional accesses made changes to the process of
instantiating controllers and sequencers. The DMA controller and
sequencer was not updated, hence this patch.
This commit is contained in:
Nilay Vaish 2011-07-26 12:20:22 -05:00
parent fb1f3bae1b
commit 00ad4eb8ce
5 changed files with 20 additions and 10 deletions
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6
configs/ruby/MESI_CMP_directory.py
View file

@ -166,11 +166,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# #
dma_seq = DMASequencer(version = i, dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port, physMemPort = system.physmem.port,
physmem = system.physmem) physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq) dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':

6
configs/ruby/MI_example.py
View file

@ -141,11 +141,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# #
dma_seq = DMASequencer(version = i, dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port, physMemPort = system.physmem.port,
physmem = system.physmem) physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq) dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':

6
configs/ruby/MOESI_CMP_directory.py
View file

@ -165,11 +165,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# #
dma_seq = DMASequencer(version = i, dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port, physMemPort = system.physmem.port,
physmem = system.physmem) physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq) dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':

6
configs/ruby/MOESI_CMP_token.py
View file

@ -189,11 +189,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# #
dma_seq = DMASequencer(version = i, dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port, physMemPort = system.physmem.port,
physmem = system.physmem) physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq) dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':

6
configs/ruby/MOESI_hammer.py
View file

@ -200,11 +200,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# #
dma_seq = DMASequencer(version = i, dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port, physMemPort = system.physmem.port,
physmem = system.physmem) physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count, cntrl_id = cntrl_count,
dma_sequencer = dma_seq) dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':