517 lines
18 KiB
C++
517 lines
18 KiB
C++
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_SPARC_REGFILE_HH__
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#define __ARCH_SPARC_REGFILE_HH__
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#include "arch/sparc/faults.hh"
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#include "sim/byteswap.hh"
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#include "sim/host.hh"
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class Checkpoint;
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namespace SparcISA
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{
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typedef uint8_t RegIndex;
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// Maximum trap level
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const int MaxTL = 4;
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//For right now, let's pretend the register file is flat
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typedef IntReg IntRegFile[NumIntRegs];
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typedef float float32_t;
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typedef double float64_t;
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//FIXME long double refers to a 10 byte float, rather than a
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//16 byte float as required. This data type may have to be emulated.
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typedef double float128_t;
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class FloatRegFile
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{
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protected:
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//Since the floating point registers overlap each other,
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//A generic storage space is used. The float to be returned is
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//pulled from the appropriate section of this region.
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char regSpace[32 * 64];
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static const int SingleWidth = 32;
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static const int DoubleWidth = 64;
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static const int QuadWidth = 128;
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public:
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FloatReg readReg(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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float32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, width);
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return htog(result32);
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case DoubleWidth:
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float64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, width);
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return htog(result64);
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case QuadWidth:
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float128_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, width);
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return htog(result128);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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}
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FloatReg readReg(int floatReg)
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{
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//Use the "natural" width of a single float
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return readReg(floatReg, SingleWidth);
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}
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FloatRegBits readRegBits(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, width);
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return htog(result32);
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case DoubleWidth:
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uint64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, width);
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return htog(result64);
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case QuadWidth:
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uint64_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, width);
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return htog(result128);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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}
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FloatRegBits readRegBits(int floatReg)
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{
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//Use the "natural" width of a single float
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return readRegBits(floatReg, SingleWidth);
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}
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Fault setReg(int floatReg, const FloatReg &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, width);
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case DoubleWidth:
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uint64_t result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, width);
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case QuadWidth:
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uint64_t result128 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result128, width);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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Fault setReg(int floatReg, const FloatReg &val)
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{
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//Use the "natural" width of a single float
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return setReg(floatReg, val, SingleWidth);
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, width);
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case DoubleWidth:
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uint64_t result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, width);
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case QuadWidth:
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uint64_t result128 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result128, width);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val)
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{
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//Use the "natural" width of a single float
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return setReg(floatReg, val, SingleWidth);
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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enum MiscRegIndex
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{
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MISCREG_PSTATE,
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MISCREG_PSTATE_AG,
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MISCREG_PSTATE_IE,
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MISCREG_PSTATE_PRIV,
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MISCREG_PSTATE_AM,
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MISCREG_PSTATE_PEF,
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MISCREG_PSTATE_RED,
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MISCREG_PSTATE_MM,
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MISCREG_PSTATE_TLE,
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MISCREG_PSTATE_CLE,
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MISCREG_TBA,
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MISCREG_Y,
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MISCREG_Y_VALUE,
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MISCREG_PIL,
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MISCREG_CWP,
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MISCREG_TT_BASE,
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MISCREG_TT_END = MISCREG_TT_BASE + MaxTL,
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MISCREG_CCR,
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MISCREG_CCR_ICC,
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MISCREG_CCR_ICC_C,
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MISCREG_CCR_ICC_V,
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MISCREG_CCR_ICC_Z,
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MISCREG_CCR_ICC_N,
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MISCREG_CCR_XCC,
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MISCREG_CCR_XCC_C,
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MISCREG_CCR_XCC_V,
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MISCREG_CCR_XCC_Z,
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MISCREG_CCR_XCC_N,
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MISCREG_ASI,
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MISCREG_TL,
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MISCREG_TPC_BASE,
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MISCREG_TPC_END = MISCREG_TPC_BASE + MaxTL,
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MISCREG_TNPC_BASE,
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MISCREG_TNPC_END = MISCREG_TNPC_BASE + MaxTL,
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MISCREG_TSTATE_BASE,
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MISCREG_TSTATE_END = MISCREG_TSTATE_BASE + MaxTL,
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MISCREG_TSTATE_CWP_BASE,
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MISCREG_TSTATE_CWP_END = MISCREG_TSTATE_CWP_BASE + MaxTL,
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MISCREG_TSTATE_PSTATE_BASE,
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MISCREG_TSTATE_PSTATE_END = MISCREG_TSTATE_PSTATE_BASE + MaxTL,
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MISCREG_TSTATE_ASI_BASE,
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MISCREG_TSTATE_ASI_END = MISCREG_TSTATE_ASI_BASE + MaxTL,
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MISCREG_TSTATE_CCR_BASE,
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MISCREG_TSTATE_CCR_END = MISCREG_TSTATE_CCR_BASE + MaxTL,
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MISCREG_TICK,
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MISCREG_TICK_COUNTER,
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MISCREG_TICK_NPT,
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MISCREG_CANSAVE,
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MISCREG_CANRESTORE,
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MISCREG_OTHERWIN,
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MISCREG_CLEANWIN,
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MISCREG_WSTATE,
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MISCREG_WSTATE_NORMAL,
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MISCREG_WSTATE_OTHER,
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MISCREG_VER,
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MISCREG_VER_MAXWIN,
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MISCREG_VER_MAXTL,
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MISCREG_VER_MASK,
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MISCREG_VER_IMPL,
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MISCREG_VER_MANUF,
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MISCREG_FSR,
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MISCREG_FSR_CEXC,
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MISCREG_FSR_CEXC_NXC,
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MISCREG_FSR_CEXC_DZC,
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MISCREG_FSR_CEXC_UFC,
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MISCREG_FSR_CEXC_OFC,
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MISCREG_FSR_CEXC_NVC,
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MISCREG_FSR_AEXC,
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MISCREG_FSR_AEXC_NXC,
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MISCREG_FSR_AEXC_DZC,
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MISCREG_FSR_AEXC_UFC,
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MISCREG_FSR_AEXC_OFC,
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MISCREG_FSR_AEXC_NVC,
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MISCREG_FSR_FCC0,
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MISCREG_FSR_QNE,
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MISCREG_FSR_FTT,
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MISCREG_FSR_VER,
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MISCREG_FSR_NS,
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MISCREG_FSR_TEM,
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MISCREG_FSR_TEM_NXM,
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MISCREG_FSR_TEM_DZM,
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MISCREG_FSR_TEM_UFM,
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MISCREG_FSR_TEM_OFM,
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MISCREG_FSR_TEM_NVM,
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MISCREG_FSR_RD,
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MISCREG_FSR_FCC1,
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MISCREG_FSR_FCC2,
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MISCREG_FSR_FCC3,
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MISCREG_FPRS,
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MISCREG_FPRS_DL,
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MISCREG_FPRS_DU,
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MISCREG_FPRS_FEF,
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numMiscRegs
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};
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// The control registers, broken out into fields
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class MiscRegFile
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{
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private:
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union
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{
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uint16_t pstate; // Process State Register
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struct
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{
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uint16_t ag:1; // Alternate Globals
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uint16_t ie:1; // Interrupt enable
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uint16_t priv:1; // Privelege mode
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uint16_t am:1; // Address mask
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uint16_t pef:1; // PSTATE enable floating-point
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uint16_t red:1; // RED (reset, error, debug) state
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uint16_t mm:2; // Memory Model
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uint16_t tle:1; // Trap little-endian
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uint16_t cle:1; // Current little-endian
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} pstateFields;
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};
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uint64_t tba; // Trap Base Address
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union
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{
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uint64_t y; // Y (used in obsolete multiplication)
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struct
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{
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uint64_t value:32; // The actual value stored in y
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uint64_t :32; // reserved bits
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} yFields;
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};
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
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// on the previous level)
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union
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{
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uint8_t ccr; // Condition Code Register
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struct
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{
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union
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{
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uint8_t icc:4; // 32-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} iccFields;
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};
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union
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{
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uint8_t xcc:4; // 64-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} xccFields;
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};
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} ccrFields;
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};
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uint8_t asi; // Address Space Identifier
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uint8_t tl; // Trap Level
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from
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// previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
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// previous trap level)
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union
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{
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uint64_t tstate[MaxTL]; // Trap State
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struct
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{
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//Values are from previous trap level
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|
|
uint64_t cwp:5; // Current Window Pointer
|
||
|
|
uint64_t :2; // Reserved bits
|
||
|
|
uint64_t pstate:10; // Process State
|
||
|
|
uint64_t :6; // Reserved bits
|
||
|
|
uint64_t asi:8; // Address Space Identifier
|
||
|
|
uint64_t ccr:8; // Condition Code Register
|
||
|
|
} tstateFields[MaxTL];
|
||
|
|
};
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t tick; // Hardware clock-tick counter
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint64_t counter:63; // Clock-tick count
|
||
|
|
uint64_t npt:1; // Non-priveleged trap
|
||
|
|
} tickFields;
|
||
|
|
};
|
||
|
|
uint8_t cansave; // Savable windows
|
||
|
|
uint8_t canrestore; // Restorable windows
|
||
|
|
uint8_t otherwin; // Other windows
|
||
|
|
uint8_t cleanwin; // Clean windows
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint8_t wstate; // Window State
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
|
||
|
|
// register window trap
|
||
|
|
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
||
|
|
// register window trap
|
||
|
|
} wstateFields;
|
||
|
|
};
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t ver; // Version
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint64_t maxwin:5; // Max CWP value
|
||
|
|
uint64_t :2; // Reserved bits
|
||
|
|
uint64_t maxtl:8; // Maximum trap level
|
||
|
|
uint64_t :8; // Reserved bits
|
||
|
|
uint64_t mask:8; // Processor mask set revision number
|
||
|
|
uint64_t impl:16; // Implementation identification number
|
||
|
|
uint64_t manuf:16; // Manufacturer code
|
||
|
|
} verFields;
|
||
|
|
};
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t fsr; // Floating-Point State Register
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t cexc:5; // Current excpetion
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint64_t nxc:1; // Inexact
|
||
|
|
uint64_t dzc:1; // Divide by zero
|
||
|
|
uint64_t ufc:1; // Underflow
|
||
|
|
uint64_t ofc:1; // Overflow
|
||
|
|
uint64_t nvc:1; // Invalid operand
|
||
|
|
} cexcFields;
|
||
|
|
};
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t aexc:5; // Accrued exception
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint64_t nxc:1; // Inexact
|
||
|
|
uint64_t dzc:1; // Divide by zero
|
||
|
|
uint64_t ufc:1; // Underflow
|
||
|
|
uint64_t ofc:1; // Overflow
|
||
|
|
uint64_t nvc:1; // Invalid operand
|
||
|
|
} aexcFields;
|
||
|
|
};
|
||
|
|
uint64_t fcc0:2; // Floating-Point condtion codes
|
||
|
|
uint64_t :1; // Reserved bits
|
||
|
|
uint64_t qne:1; // Deferred trap queue not empty
|
||
|
|
// with no queue, it should read 0
|
||
|
|
uint64_t ftt:3; // Floating-Point trap type
|
||
|
|
uint64_t ver:3; // Version (of the FPU)
|
||
|
|
uint64_t :2; // Reserved bits
|
||
|
|
uint64_t ns:1; // Nonstandard floating point
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint64_t tem:5; // Trap Enable Mask
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint64_t nxm:1; // Inexact
|
||
|
|
uint64_t dzm:1; // Divide by zero
|
||
|
|
uint64_t ufm:1; // Underflow
|
||
|
|
uint64_t ofm:1; // Overflow
|
||
|
|
uint64_t nvm:1; // Invalid operand
|
||
|
|
} temFields;
|
||
|
|
};
|
||
|
|
uint64_t :2; // Reserved bits
|
||
|
|
uint64_t rd:2; // Rounding direction
|
||
|
|
uint64_t fcc1:2; // Floating-Point condition codes
|
||
|
|
uint64_t fcc2:2; // Floating-Point condition codes
|
||
|
|
uint64_t fcc3:2; // Floating-Point condition codes
|
||
|
|
uint64_t :26; // Reserved bits
|
||
|
|
} fsrFields;
|
||
|
|
};
|
||
|
|
union
|
||
|
|
{
|
||
|
|
uint8_t fprs; // Floating-Point Register State
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
uint8_t dl:1; // Dirty lower
|
||
|
|
uint8_t du:1; // Dirty upper
|
||
|
|
uint8_t fef:1; // FPRS enable floating-Point
|
||
|
|
} fprsFields;
|
||
|
|
};
|
||
|
|
|
||
|
|
public:
|
||
|
|
MiscReg readReg(int miscReg);
|
||
|
|
|
||
|
|
MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
|
||
|
|
|
||
|
|
Fault setReg(int miscReg, const MiscReg &val);
|
||
|
|
|
||
|
|
Fault setRegWithEffect(int miscReg, const MiscReg &val,
|
||
|
|
ExecContext *xc);
|
||
|
|
|
||
|
|
void serialize(std::ostream & os);
|
||
|
|
|
||
|
|
void unserialize(Checkpoint * cp, const std::string & section);
|
||
|
|
|
||
|
|
void copyMiscRegs(ExecContext * xc);
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef union
|
||
|
|
{
|
||
|
|
IntReg intreg;
|
||
|
|
FloatReg fpreg;
|
||
|
|
MiscReg ctrlreg;
|
||
|
|
} AnyReg;
|
||
|
|
|
||
|
|
struct RegFile
|
||
|
|
{
|
||
|
|
IntRegFile intRegFile; // (signed) integer register file
|
||
|
|
FloatRegFile floatRegFile; // floating point register file
|
||
|
|
MiscRegFile miscRegs; // control register file
|
||
|
|
|
||
|
|
Addr pc; // Program Counter
|
||
|
|
Addr npc; // Next Program Counter
|
||
|
|
Addr nnpc;
|
||
|
|
|
||
|
|
void serialize(std::ostream &os);
|
||
|
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace SparcISA
|
||
|
|
|
||
|
|
#endif
|