622 lines
11 KiB
INI
622 lines
11 KiB
INI
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[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[exetrace]
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intel_format=false
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legion_lockstep=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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print_data=true
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print_effaddr=true
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print_fetchseq=false
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print_iregs=false
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print_opclass=true
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print_thread=true
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speculative=true
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trace_system=client
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[serialize]
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count=10
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cycle=0
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dir=cpt.%012d
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period=0
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[stats]
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descriptions=true
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dump_cycle=0
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dump_period=0
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dump_reset=false
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ignore_events=
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mysql_db=
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mysql_host=
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mysql_password=
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mysql_user=
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_compat=true
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text_file=m5stats.txt
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
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mem_mode=timing
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physmem=system.physmem
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[system.cpu0]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port
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test=system.cpu0.l1c.cpu_side
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[system.cpu0.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu0.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.test
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mem_side=system.toL2Bus.port[1]
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[system.cpu0.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu1]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.functional
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test=system.cpu1.l1c.cpu_side
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[system.cpu1.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu1.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.test
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mem_side=system.toL2Bus.port[2]
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[system.cpu1.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu2]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.functional
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test=system.cpu2.l1c.cpu_side
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[system.cpu2.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu2.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.test
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mem_side=system.toL2Bus.port[3]
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[system.cpu2.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu3]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.functional
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test=system.cpu3.l1c.cpu_side
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[system.cpu3.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu3.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu3.test
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mem_side=system.toL2Bus.port[4]
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[system.cpu3.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu4]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.functional
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test=system.cpu4.l1c.cpu_side
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[system.cpu4.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu4.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu4.test
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mem_side=system.toL2Bus.port[5]
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[system.cpu4.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu5]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.functional
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test=system.cpu5.l1c.cpu_side
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[system.cpu5.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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||
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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||
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prefetch_latency=10
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prefetch_miss=false
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||
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prefetch_past_page=false
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prefetch_policy=none
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||
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prefetch_serial_squash=false
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||
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prefetch_use_cpu_id=true
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||
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prefetcher_size=100
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||
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prioritizeRequests=false
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||
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protocol=system.cpu5.l1c.protocol
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||
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repl=Null
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||
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size=32768
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||
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split=false
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||
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split_size=0
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||
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store_compressed=false
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||
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subblock_size=0
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||
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tgts_per_mshr=8
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||
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trace_addr=0
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||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu5.test
|
||
|
|
mem_side=system.toL2Bus.port[6]
|
||
|
|
|
||
|
|
[system.cpu5.l1c.protocol]
|
||
|
|
type=CoherenceProtocol
|
||
|
|
do_upgrades=true
|
||
|
|
protocol=moesi
|
||
|
|
|
||
|
|
[system.cpu6]
|
||
|
|
type=MemTest
|
||
|
|
children=l1c
|
||
|
|
atomic=false
|
||
|
|
max_loads=100000
|
||
|
|
memory_size=65536
|
||
|
|
percent_dest_unaligned=50
|
||
|
|
percent_functional=50
|
||
|
|
percent_reads=65
|
||
|
|
percent_source_unaligned=50
|
||
|
|
percent_uncacheable=10
|
||
|
|
progress_interval=10000
|
||
|
|
trace_addr=0
|
||
|
|
functional=system.funcmem.functional
|
||
|
|
test=system.cpu6.l1c.cpu_side
|
||
|
|
|
||
|
|
[system.cpu6.l1c]
|
||
|
|
type=BaseCache
|
||
|
|
children=protocol
|
||
|
|
adaptive_compression=false
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
compressed_bus=false
|
||
|
|
compression_latency=0
|
||
|
|
hash_delay=1
|
||
|
|
hit_latency=1
|
||
|
|
latency=1
|
||
|
|
lifo=false
|
||
|
|
max_miss_count=0
|
||
|
|
mshrs=12
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
protocol=system.cpu6.l1c.protocol
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
split=false
|
||
|
|
split_size=0
|
||
|
|
store_compressed=false
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu6.test
|
||
|
|
mem_side=system.toL2Bus.port[7]
|
||
|
|
|
||
|
|
[system.cpu6.l1c.protocol]
|
||
|
|
type=CoherenceProtocol
|
||
|
|
do_upgrades=true
|
||
|
|
protocol=moesi
|
||
|
|
|
||
|
|
[system.cpu7]
|
||
|
|
type=MemTest
|
||
|
|
children=l1c
|
||
|
|
atomic=false
|
||
|
|
max_loads=100000
|
||
|
|
memory_size=65536
|
||
|
|
percent_dest_unaligned=50
|
||
|
|
percent_functional=50
|
||
|
|
percent_reads=65
|
||
|
|
percent_source_unaligned=50
|
||
|
|
percent_uncacheable=10
|
||
|
|
progress_interval=10000
|
||
|
|
trace_addr=0
|
||
|
|
functional=system.funcmem.functional
|
||
|
|
test=system.cpu7.l1c.cpu_side
|
||
|
|
|
||
|
|
[system.cpu7.l1c]
|
||
|
|
type=BaseCache
|
||
|
|
children=protocol
|
||
|
|
adaptive_compression=false
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
compressed_bus=false
|
||
|
|
compression_latency=0
|
||
|
|
hash_delay=1
|
||
|
|
hit_latency=1
|
||
|
|
latency=1
|
||
|
|
lifo=false
|
||
|
|
max_miss_count=0
|
||
|
|
mshrs=12
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
protocol=system.cpu7.l1c.protocol
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
split=false
|
||
|
|
split_size=0
|
||
|
|
store_compressed=false
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu7.test
|
||
|
|
mem_side=system.toL2Bus.port[8]
|
||
|
|
|
||
|
|
[system.cpu7.l1c.protocol]
|
||
|
|
type=CoherenceProtocol
|
||
|
|
do_upgrades=true
|
||
|
|
protocol=moesi
|
||
|
|
|
||
|
|
[system.funcmem]
|
||
|
|
type=PhysicalMemory
|
||
|
|
file=
|
||
|
|
latency=1
|
||
|
|
range=0:134217727
|
||
|
|
zero=false
|
||
|
|
functional=system.cpu7.functional
|
||
|
|
port=system.cpu0.functional
|
||
|
|
|
||
|
|
[system.l2c]
|
||
|
|
type=BaseCache
|
||
|
|
adaptive_compression=false
|
||
|
|
assoc=8
|
||
|
|
block_size=64
|
||
|
|
compressed_bus=false
|
||
|
|
compression_latency=0
|
||
|
|
hash_delay=1
|
||
|
|
hit_latency=1
|
||
|
|
latency=10
|
||
|
|
lifo=false
|
||
|
|
max_miss_count=0
|
||
|
|
mshrs=92
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
protocol=Null
|
||
|
|
repl=Null
|
||
|
|
size=65536
|
||
|
|
split=false
|
||
|
|
split_size=0
|
||
|
|
store_compressed=false
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=16
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.toL2Bus.port[0]
|
||
|
|
mem_side=system.membus.port[0]
|
||
|
|
|
||
|
|
[system.membus]
|
||
|
|
type=Bus
|
||
|
|
bus_id=0
|
||
|
|
clock=2
|
||
|
|
responder_set=false
|
||
|
|
width=16
|
||
|
|
port=system.l2c.mem_side system.physmem.port
|
||
|
|
|
||
|
|
[system.physmem]
|
||
|
|
type=PhysicalMemory
|
||
|
|
file=
|
||
|
|
latency=1
|
||
|
|
range=0:134217727
|
||
|
|
zero=false
|
||
|
|
port=system.membus.port[1]
|
||
|
|
|
||
|
|
[system.toL2Bus]
|
||
|
|
type=Bus
|
||
|
|
bus_id=0
|
||
|
|
clock=2
|
||
|
|
responder_set=false
|
||
|
|
width=16
|
||
|
|
port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||
|
|
|
||
|
|
[trace]
|
||
|
|
bufsize=0
|
||
|
|
cycle=0
|
||
|
|
dump_on_exit=false
|
||
|
|
file=cout
|
||
|
|
flags=
|
||
|
|
ignore=
|
||
|
|
start=0
|
||
|
|
|