2006-10-12 21:04:14 +02:00
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---------- Begin Simulation Statistics ----------
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2006-12-05 01:07:00 +01:00
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host_inst_rate 471701 # Simulator instruction rate (inst/s)
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host_mem_usage 255440 # Number of bytes of host memory used
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host_seconds 187.33 # Real time elapsed on the host
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host_tick_rate 6446013 # Simulator tick rate (ticks/s)
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2006-10-12 21:04:14 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2006-12-05 01:07:00 +01:00
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sim_insts 88361899 # Number of instructions simulated
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sim_seconds 0.001208 # Number of seconds simulated
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sim_ticks 1207510003 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.overall_hits 34696923 # number of overall hits
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system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 200145 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.replacements 196049 # number of replacements
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system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use
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system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 147135 # number of writebacks
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system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2006-12-05 01:07:00 +01:00
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system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
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system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses
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system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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2006-12-05 01:07:00 +01:00
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system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2006-12-05 01:07:00 +01:00
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system.cpu.icache.overall_hits 88285387 # number of overall hits
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system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses
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system.cpu.icache.overall_misses 76513 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2006-12-05 01:07:00 +01:00
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system.cpu.icache.replacements 74468 # number of replacements
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system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2006-12-05 01:07:00 +01:00
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system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use
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system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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2006-12-05 01:07:00 +01:00
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses
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|
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system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles
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|
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses
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system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses)
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system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits
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system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses
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system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses
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system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses
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system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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|
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-12-05 01:07:00 +01:00
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system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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|
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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|
|
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-12-05 01:07:00 +01:00
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|
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system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses
|
|
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system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
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|
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_hits 254770 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 169023 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.replacements 135670 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 115647 # number of writebacks
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.numCycles 1207510003 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.num_insts 88361899 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 35229376 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
