2010-06-02 19:58:01 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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2009-06-22 02:21:25 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_MACROMEM_HH__
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#define __ARCH_ARM_MACROMEM_HH__
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#include "arch/arm/insts/pred_inst.hh"
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2010-06-02 19:58:10 +02:00
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#include "arch/arm/tlb.hh"
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2009-06-22 02:21:25 +02:00
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namespace ArmISA
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{
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static inline unsigned int
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number_of_ones(int32_t val)
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{
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uint32_t ones = 0;
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for (int i = 0; i < 32; i++ )
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{
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if ( val & (1<<i) )
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ones++;
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}
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return ones;
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}
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2010-06-02 19:58:18 +02:00
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/**
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* Base class for Memory microops
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*/
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2010-06-02 19:58:12 +02:00
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class MicroOp : public PredOp
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{
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protected:
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MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
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: PredOp(mnem, machInst, __opClass)
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{
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}
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public:
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void
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setDelayedCommit()
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{
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flags[IsDelayedCommit] = true;
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}
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};
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2009-07-09 08:02:19 +02:00
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/**
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* Microops of the form IntRegA = IntRegB op Imm
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*/
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2010-06-02 19:58:12 +02:00
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class MicroIntOp : public MicroOp
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2009-07-09 08:02:19 +02:00
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{
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protected:
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RegIndex ura, urb;
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uint8_t imm;
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MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, uint8_t _imm)
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2010-06-02 19:58:12 +02:00
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), imm(_imm)
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{
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}
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2010-08-23 18:18:42 +02:00
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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2009-07-09 08:02:19 +02:00
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};
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2009-07-09 08:02:19 +02:00
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/**
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* Memory microops which use IntReg + Imm addressing
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*/
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class MicroMemOp : public MicroIntOp
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{
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protected:
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bool up;
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unsigned memAccessFlags;
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MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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2010-06-02 19:58:02 +02:00
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RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
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2009-07-09 08:02:19 +02:00
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: MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
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2010-06-02 19:58:10 +02:00
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up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
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2009-07-09 08:02:19 +02:00
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{
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}
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2010-08-23 18:18:42 +02:00
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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2009-07-09 08:02:19 +02:00
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};
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2010-06-02 19:58:18 +02:00
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/**
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* Base class for microcoded integer memory instructions.
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*/
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2010-06-02 19:58:03 +02:00
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class MacroMemOp : public PredMacroOp
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{
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protected:
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MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex rn, bool index, bool up, bool user,
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bool writeback, bool load, uint32_t reglist);
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};
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2010-06-02 19:58:18 +02:00
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/**
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* Base class for microcoded floating point memory instructions.
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*/
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2010-06-02 19:58:04 +02:00
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class MacroVFPMemOp : public PredMacroOp
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{
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protected:
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MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex rn, RegIndex vd, bool single, bool up,
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bool writeback, bool load, uint32_t offset);
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};
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2009-06-22 02:21:25 +02:00
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}
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#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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