94 lines
3.2 KiB
INI
94 lines
3.2 KiB
INI
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# Copyright (c) 2012 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Dam Sunwoo
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#
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# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py
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#
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# Stats grouped together will show as grouped in Streamline.
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# E.g.,
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#
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# icache =
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# icache.overall_hits::total
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# icache.overall_misses::total
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#
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# will display the icache as a stacked line chart.
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# Charts will still be configurable in Streamline.
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[PER_CPU_STATS]
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# "system.cpu#." will automatically prepended for per-CPU stats
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cycles =
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num_busy_cycles
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num_idle_cycles
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register_access =
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num_int_register_reads
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num_int_register_writes
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mem_refs =
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num_mem_refs
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inst_breakdown =
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num_conditional_control_insts
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num_int_insts
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num_fp_insts
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num_load_insts
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num_store_insts
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icache =
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icache.overall_hits::total
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icache.overall_misses::total
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dcache =
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dcache.overall_hits::total
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dcache.overall_misses::total
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[PER_SWITCHCPU_STATS]
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# If starting from checkpoints, gem5 keeps CPU stats in system.switch_cpus# structures.
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# List per-switchcpu stats here if any
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# "system.switch_cpus#" will automatically prepended for per-CPU stats
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[PER_L2_STATS]
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l2 =
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overall_hits::total
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overall_misses::total
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[OTHER_STATS]
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physmem =
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system.physmem.bw_total::total
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