515 lines
9.7 KiB
INI
515 lines
9.7 KiB
INI
|
[root]
|
||
|
|
type=Root
|
||
|
|
children=system
|
||
|
|
dummy=0
|
||
|
|
|
||
|
|
[system]
|
||
|
|
type=System
|
||
|
|
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
|
||
|
|
mem_mode=timing
|
||
|
|
physmem=system.physmem
|
||
|
|
|
||
|
|
[system.cpu0]
|
||
|
|
type=TimingSimpleCPU
|
||
|
|
children=dcache dtb icache itb tracer workload
|
||
|
|
clock=500
|
||
|
|
cpu_id=0
|
||
|
|
defer_registration=false
|
||
|
|
dtb=system.cpu0.dtb
|
||
|
|
function_trace=false
|
||
|
|
function_trace_start=0
|
||
|
|
itb=system.cpu0.itb
|
||
|
|
max_insts_all_threads=0
|
||
|
|
max_insts_any_thread=500000
|
||
|
|
max_loads_all_threads=0
|
||
|
|
max_loads_any_thread=0
|
||
|
|
numThreads=1
|
||
|
|
phase=0
|
||
|
|
progress_interval=0
|
||
|
|
system=system
|
||
|
|
tracer=system.cpu0.tracer
|
||
|
|
workload=system.cpu0.workload
|
||
|
|
dcache_port=system.cpu0.dcache.cpu_side
|
||
|
|
icache_port=system.cpu0.icache.cpu_side
|
||
|
|
|
||
|
|
[system.cpu0.dcache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu0.dcache_port
|
||
|
|
mem_side=system.toL2Bus.port[2]
|
||
|
|
|
||
|
|
[system.cpu0.dtb]
|
||
|
|
type=AlphaDTB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu0.icache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=1
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu0.icache_port
|
||
|
|
mem_side=system.toL2Bus.port[1]
|
||
|
|
|
||
|
|
[system.cpu0.itb]
|
||
|
|
type=AlphaITB
|
||
|
|
size=48
|
||
|
|
|
||
|
|
[system.cpu0.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
|
||
|
|
[system.cpu0.workload]
|
||
|
|
type=EioProcess
|
||
|
|
chkpt=
|
||
|
|
errout=cerr
|
||
|
|
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||
|
|
input=None
|
||
|
|
max_stack_size=67108864
|
||
|
|
output=cout
|
||
|
|
system=system
|
||
|
|
|
||
|
|
[system.cpu1]
|
||
|
|
type=TimingSimpleCPU
|
||
|
|
children=dcache dtb icache itb tracer workload
|
||
|
|
clock=500
|
||
|
|
cpu_id=1
|
||
|
|
defer_registration=false
|
||
|
|
dtb=system.cpu1.dtb
|
||
|
|
function_trace=false
|
||
|
|
function_trace_start=0
|
||
|
|
itb=system.cpu1.itb
|
||
|
|
max_insts_all_threads=0
|
||
|
|
max_insts_any_thread=500000
|
||
|
|
max_loads_all_threads=0
|
||
|
|
max_loads_any_thread=0
|
||
|
|
numThreads=1
|
||
|
|
phase=0
|
||
|
|
progress_interval=0
|
||
|
|
system=system
|
||
|
|
tracer=system.cpu1.tracer
|
||
|
|
workload=system.cpu1.workload
|
||
|
|
dcache_port=system.cpu1.dcache.cpu_side
|
||
|
|
icache_port=system.cpu1.icache.cpu_side
|
||
|
|
|
||
|
|
[system.cpu1.dcache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu1.dcache_port
|
||
|
|
mem_side=system.toL2Bus.port[4]
|
||
|
|
|
||
|
|
[system.cpu1.dtb]
|
||
|
|
type=AlphaDTB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu1.icache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=1
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu1.icache_port
|
||
|
|
mem_side=system.toL2Bus.port[3]
|
||
|
|
|
||
|
|
[system.cpu1.itb]
|
||
|
|
type=AlphaITB
|
||
|
|
size=48
|
||
|
|
|
||
|
|
[system.cpu1.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
|
||
|
|
[system.cpu1.workload]
|
||
|
|
type=EioProcess
|
||
|
|
chkpt=
|
||
|
|
errout=cerr
|
||
|
|
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||
|
|
input=None
|
||
|
|
max_stack_size=67108864
|
||
|
|
output=cout
|
||
|
|
system=system
|
||
|
|
|
||
|
|
[system.cpu2]
|
||
|
|
type=TimingSimpleCPU
|
||
|
|
children=dcache dtb icache itb tracer workload
|
||
|
|
clock=500
|
||
|
|
cpu_id=2
|
||
|
|
defer_registration=false
|
||
|
|
dtb=system.cpu2.dtb
|
||
|
|
function_trace=false
|
||
|
|
function_trace_start=0
|
||
|
|
itb=system.cpu2.itb
|
||
|
|
max_insts_all_threads=0
|
||
|
|
max_insts_any_thread=500000
|
||
|
|
max_loads_all_threads=0
|
||
|
|
max_loads_any_thread=0
|
||
|
|
numThreads=1
|
||
|
|
phase=0
|
||
|
|
progress_interval=0
|
||
|
|
system=system
|
||
|
|
tracer=system.cpu2.tracer
|
||
|
|
workload=system.cpu2.workload
|
||
|
|
dcache_port=system.cpu2.dcache.cpu_side
|
||
|
|
icache_port=system.cpu2.icache.cpu_side
|
||
|
|
|
||
|
|
[system.cpu2.dcache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu2.dcache_port
|
||
|
|
mem_side=system.toL2Bus.port[6]
|
||
|
|
|
||
|
|
[system.cpu2.dtb]
|
||
|
|
type=AlphaDTB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu2.icache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=1
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu2.icache_port
|
||
|
|
mem_side=system.toL2Bus.port[5]
|
||
|
|
|
||
|
|
[system.cpu2.itb]
|
||
|
|
type=AlphaITB
|
||
|
|
size=48
|
||
|
|
|
||
|
|
[system.cpu2.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
|
||
|
|
[system.cpu2.workload]
|
||
|
|
type=EioProcess
|
||
|
|
chkpt=
|
||
|
|
errout=cerr
|
||
|
|
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||
|
|
input=None
|
||
|
|
max_stack_size=67108864
|
||
|
|
output=cout
|
||
|
|
system=system
|
||
|
|
|
||
|
|
[system.cpu3]
|
||
|
|
type=TimingSimpleCPU
|
||
|
|
children=dcache dtb icache itb tracer workload
|
||
|
|
clock=500
|
||
|
|
cpu_id=3
|
||
|
|
defer_registration=false
|
||
|
|
dtb=system.cpu3.dtb
|
||
|
|
function_trace=false
|
||
|
|
function_trace_start=0
|
||
|
|
itb=system.cpu3.itb
|
||
|
|
max_insts_all_threads=0
|
||
|
|
max_insts_any_thread=500000
|
||
|
|
max_loads_all_threads=0
|
||
|
|
max_loads_any_thread=0
|
||
|
|
numThreads=1
|
||
|
|
phase=0
|
||
|
|
progress_interval=0
|
||
|
|
system=system
|
||
|
|
tracer=system.cpu3.tracer
|
||
|
|
workload=system.cpu3.workload
|
||
|
|
dcache_port=system.cpu3.dcache.cpu_side
|
||
|
|
icache_port=system.cpu3.icache.cpu_side
|
||
|
|
|
||
|
|
[system.cpu3.dcache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=4
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu3.dcache_port
|
||
|
|
mem_side=system.toL2Bus.port[8]
|
||
|
|
|
||
|
|
[system.cpu3.dtb]
|
||
|
|
type=AlphaDTB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu3.icache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=1
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu3.icache_port
|
||
|
|
mem_side=system.toL2Bus.port[7]
|
||
|
|
|
||
|
|
[system.cpu3.itb]
|
||
|
|
type=AlphaITB
|
||
|
|
size=48
|
||
|
|
|
||
|
|
[system.cpu3.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
|
||
|
|
[system.cpu3.workload]
|
||
|
|
type=EioProcess
|
||
|
|
chkpt=
|
||
|
|
errout=cerr
|
||
|
|
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||
|
|
input=None
|
||
|
|
max_stack_size=67108864
|
||
|
|
output=cout
|
||
|
|
system=system
|
||
|
|
|
||
|
|
[system.l2c]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=8
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=10000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=92
|
||
|
|
prefetch_access=false
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=100000
|
||
|
|
prefetch_miss=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=4194304
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=16
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.toL2Bus.port[0]
|
||
|
|
mem_side=system.membus.port[0]
|
||
|
|
|
||
|
|
[system.membus]
|
||
|
|
type=Bus
|
||
|
|
block_size=64
|
||
|
|
bus_id=0
|
||
|
|
clock=1000
|
||
|
|
header_cycles=1
|
||
|
|
responder_set=false
|
||
|
|
width=64
|
||
|
|
port=system.l2c.mem_side system.physmem.port[0]
|
||
|
|
|
||
|
|
[system.physmem]
|
||
|
|
type=PhysicalMemory
|
||
|
|
file=
|
||
|
|
latency=30000
|
||
|
|
latency_var=0
|
||
|
|
null=false
|
||
|
|
range=0:134217727
|
||
|
|
zero=false
|
||
|
|
port=system.membus.port[1]
|
||
|
|
|
||
|
|
[system.toL2Bus]
|
||
|
|
type=Bus
|
||
|
|
block_size=64
|
||
|
|
bus_id=0
|
||
|
|
clock=1000
|
||
|
|
header_cycles=1
|
||
|
|
responder_set=false
|
||
|
|
width=64
|
||
|
|
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||
|
|
|