2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2010-08-26 02:10:42 +02:00
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host_inst_rate 1674821 # Simulator instruction rate (inst/s)
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host_mem_usage 210020 # Number of bytes of host memory used
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host_seconds 357.42 # Real time elapsed on the host
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host_tick_rate 2260963263 # Simulator tick rate (ticks/s)
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2010-07-27 07:03:44 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2010-08-26 02:10:42 +02:00
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sim_insts 598619824 # Number of instructions simulated
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2010-07-27 07:03:44 +02:00
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sim_seconds 0.808121 # Number of seconds simulated
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sim_ticks 808121048000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 216713991 # number of overall hits
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system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 498477 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 433495 # number of replacements
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system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use
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system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 305427 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 570070553 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 570069910 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 886578.398134 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 570070553 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
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system.cpu.icache.demand_hits 570069910 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 570069910 # number of overall hits
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system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_misses 643 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 12 # number of replacements
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system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use
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system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles
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|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 157466 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 280768 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 81265 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 61092 # number of writebacks
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.numCycles 1616242096 # number of cpu cycles simulated
|
2010-08-26 02:10:42 +02:00
|
|
|
system.cpu.num_insts 598619824 # Number of instructions executed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.num_refs 219174038 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
