2009-05-11 19:38:43 +02:00
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* CacheMemory.h
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*
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* Description:
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*
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* $Id: CacheMemory.h,v 3.7 2004/06/18 20:15:15 beckmann Exp $
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*
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*/
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#ifndef CACHEMEMORY_H
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#define CACHEMEMORY_H
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2009-05-11 19:38:45 +02:00
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#include "mem/ruby/slicc_interface/AbstractChip.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/recorder/CacheRecorder.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/gems_common/Vector.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
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#include "mem/ruby/system/PseudoLRUPolicy.hh"
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#include "mem/ruby/system/LRUPolicy.hh"
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2009-05-11 19:38:43 +02:00
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#include <vector>
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template<class ENTRY>
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class CacheMemory {
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public:
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// Constructors
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CacheMemory(AbstractChip* chip_ptr, int numSetBits, int cacheAssoc, const MachineType machType, const string& description);
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// Destructor
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~CacheMemory();
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// Public Methods
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void printConfig(ostream& out);
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// perform a cache access and see if we hit or not. Return true on a hit.
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bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
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// similar to above, but doesn't require full access check
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bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
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// tests to see if an address is present in the cache
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bool isTagPresent(const Address& address) const;
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool cacheAvail(const Address& address) const;
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// find an unused entry and sets the tag appropriate for the address
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void allocate(const Address& address);
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// Explicitly free up this address
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void deallocate(const Address& address);
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// Returns with the physical address of the conflicting cache line
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Address cacheProbe(const Address& address) const;
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// looks an address up in the cache
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ENTRY& lookup(const Address& address);
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const ENTRY& lookup(const Address& address) const;
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// Get/Set permission of cache block
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AccessPermission getPermission(const Address& address) const;
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void changePermission(const Address& address, AccessPermission new_perm);
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// Hook for checkpointing the contents of the cache
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void recordCacheContents(CacheRecorder& tr) const;
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void setAsInstructionCache(bool is_icache) { m_is_instruction_cache = is_icache; }
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// Set this address to most recently used
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void setMRU(const Address& address);
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void getMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes );
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void setMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes );
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// Print cache contents
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void print(ostream& out) const;
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void printData(ostream& out) const;
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private:
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// Private Methods
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// convert a Address to its location in the cache
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Index addressToCacheSet(const Address& address) const;
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// Given a cache tag: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int findTagInSet(Index line, const Address& tag) const;
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int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const;
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// Private copy constructor and assignment operator
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CacheMemory(const CacheMemory& obj);
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CacheMemory& operator=(const CacheMemory& obj);
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// Data Members (m_prefix)
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AbstractChip* m_chip_ptr;
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MachineType m_machType;
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string m_description;
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bool m_is_instruction_cache;
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// The first index is the # of cache lines.
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// The second index is the the amount associativity.
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Vector<Vector<ENTRY> > m_cache;
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AbstractReplacementPolicy *m_replacementPolicy_ptr;
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int m_cache_num_sets;
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int m_cache_num_set_bits;
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int m_cache_assoc;
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};
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// Output operator declaration
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//ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
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// ******************* Definitions *******************
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// Output operator definition
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template<class ENTRY>
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inline
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ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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// ****************************************************************
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template<class ENTRY>
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inline
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CacheMemory<ENTRY>::CacheMemory(AbstractChip* chip_ptr, int numSetBits,
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int cacheAssoc, const MachineType machType, const string& description)
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{
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//cout << "CacheMemory constructor numThreads = " << numThreads << endl;
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m_chip_ptr = chip_ptr;
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m_machType = machType;
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m_description = MachineType_to_string(m_machType)+"_"+description;
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m_cache_num_set_bits = numSetBits;
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m_cache_num_sets = 1 << numSetBits;
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m_cache_assoc = cacheAssoc;
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m_is_instruction_cache = false;
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m_cache.setSize(m_cache_num_sets);
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if(strcmp(g_REPLACEMENT_POLICY, "PSEDUO_LRU") == 0)
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m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
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else if(strcmp(g_REPLACEMENT_POLICY, "LRU") == 0)
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m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc);
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else
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assert(false);
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for (int i = 0; i < m_cache_num_sets; i++) {
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m_cache[i].setSize(m_cache_assoc);
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for (int j = 0; j < m_cache_assoc; j++) {
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m_cache[i][j].m_Address.setAddress(0);
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m_cache[i][j].m_Permission = AccessPermission_NotPresent;
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}
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}
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// cout << "Before setting trans address list size" << endl;
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//create a trans address for each SMT thread
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// m_trans_address_list.setSize(numThreads);
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// for(int i=0; i < numThreads; ++i){
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// cout << "Setting list size for list " << i << endl;
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// m_trans_address_list[i].setSize(30);
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// }
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//cout << "CacheMemory constructor finished" << endl;
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}
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template<class ENTRY>
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inline
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CacheMemory<ENTRY>::~CacheMemory()
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{
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if(m_replacementPolicy_ptr != NULL)
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delete m_replacementPolicy_ptr;
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}
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template<class ENTRY>
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inline
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void CacheMemory<ENTRY>::printConfig(ostream& out)
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{
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out << "Cache config: " << m_description << endl;
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out << " cache_associativity: " << m_cache_assoc << endl;
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out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl;
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const int cache_num_sets = 1 << m_cache_num_set_bits;
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out << " num_cache_sets: " << cache_num_sets << endl;
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out << " cache_set_size_bytes: " << cache_num_sets * RubyConfig::dataBlockBytes() << endl;
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out << " cache_set_size_Kbytes: "
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<< double(cache_num_sets * RubyConfig::dataBlockBytes()) / (1<<10) << endl;
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out << " cache_set_size_Mbytes: "
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<< double(cache_num_sets * RubyConfig::dataBlockBytes()) / (1<<20) << endl;
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out << " cache_size_bytes: "
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<< cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc << endl;
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out << " cache_size_Kbytes: "
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<< double(cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc) / (1<<10) << endl;
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out << " cache_size_Mbytes: "
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<< double(cache_num_sets * RubyConfig::dataBlockBytes() * m_cache_assoc) / (1<<20) << endl;
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}
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// PRIVATE METHODS
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// convert a Address to its location in the cache
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template<class ENTRY>
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inline
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Index CacheMemory<ENTRY>::addressToCacheSet(const Address& address) const
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{
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assert(address == line_address(address));
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Index temp = -1;
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switch (m_machType) {
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case MACHINETYPE_L1CACHE_ENUM:
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temp = map_address_to_L1CacheSet(address, m_cache_num_set_bits);
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break;
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case MACHINETYPE_L2CACHE_ENUM:
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temp = map_address_to_L2CacheSet(address, m_cache_num_set_bits);
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break;
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default:
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ERROR_MSG("Don't recognize m_machType");
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}
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assert(temp < m_cache_num_sets);
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assert(temp >= 0);
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return temp;
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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template<class ENTRY>
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inline
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int CacheMemory<ENTRY>::findTagInSet(Index cacheSet, const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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for (int i=0; i < m_cache_assoc; i++) {
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if ((m_cache[cacheSet][i].m_Address == tag) &&
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(m_cache[cacheSet][i].m_Permission != AccessPermission_NotPresent)) {
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return i;
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}
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}
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return -1; // Not found
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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template<class ENTRY>
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inline
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int CacheMemory<ENTRY>::findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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for (int i=0; i < m_cache_assoc; i++) {
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if (m_cache[cacheSet][i].m_Address == tag)
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return i;
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}
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return -1; // Not found
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}
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// PUBLIC METHODS
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template<class ENTRY>
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inline
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bool CacheMemory<ENTRY>::tryCacheAccess(const Address& address,
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CacheRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc != -1){ // Do we even have a tag match?
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ENTRY& entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry.getDataBlk());
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if(entry.m_Permission == AccessPermission_Read_Write) {
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return true;
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}
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if ((entry.m_Permission == AccessPermission_Read_Only) &&
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(type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
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return true;
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}
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// The line must not be accessible
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}
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data_ptr = NULL;
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return false;
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}
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template<class ENTRY>
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inline
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bool CacheMemory<ENTRY>::testCacheAccess(const Address& address,
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CacheRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc != -1){ // Do we even have a tag match?
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ENTRY& entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry.getDataBlk());
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return (m_cache[cacheSet][loc].m_Permission != AccessPermission_NotPresent);
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}
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data_ptr = NULL;
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return false;
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}
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// tests to see if an address is present in the cache
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template<class ENTRY>
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inline
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bool CacheMemory<ENTRY>::isTagPresent(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int location = findTagInSet(cacheSet, address);
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if (location == -1) {
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// We didn't find the tag
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DEBUG_EXPR(CACHE_COMP, LowPrio, address);
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DEBUG_MSG(CACHE_COMP, LowPrio, "No tag match");
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return false;
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}
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DEBUG_EXPR(CACHE_COMP, LowPrio, address);
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DEBUG_MSG(CACHE_COMP, LowPrio, "found");
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return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Returns true if there is:
|
|
|
|
// a) a tag match on this address or there is
|
|
|
|
// b) an unused line in the same cache "way"
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
bool CacheMemory<ENTRY>::cacheAvail(const Address& address) const
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
|
|
|
|
Index cacheSet = addressToCacheSet(address);
|
|
|
|
|
|
|
|
for (int i=0; i < m_cache_assoc; i++) {
|
|
|
|
if (m_cache[cacheSet][i].m_Address == address) {
|
|
|
|
// Already in the cache
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (m_cache[cacheSet][i].m_Permission == AccessPermission_NotPresent) {
|
|
|
|
// We found an empty entry
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::allocate(const Address& address)
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
assert(!isTagPresent(address));
|
|
|
|
assert(cacheAvail(address));
|
|
|
|
DEBUG_EXPR(CACHE_COMP, HighPrio, address);
|
|
|
|
|
|
|
|
// Find the first open slot
|
|
|
|
Index cacheSet = addressToCacheSet(address);
|
|
|
|
for (int i=0; i < m_cache_assoc; i++) {
|
|
|
|
if (m_cache[cacheSet][i].m_Permission == AccessPermission_NotPresent) {
|
|
|
|
m_cache[cacheSet][i] = ENTRY(); // Init entry
|
|
|
|
m_cache[cacheSet][i].m_Address = address;
|
|
|
|
m_cache[cacheSet][i].m_Permission = AccessPermission_Invalid;
|
|
|
|
|
|
|
|
m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ERROR_MSG("Allocate didn't find an available entry");
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::deallocate(const Address& address)
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
assert(isTagPresent(address));
|
|
|
|
DEBUG_EXPR(CACHE_COMP, HighPrio, address);
|
|
|
|
lookup(address).m_Permission = AccessPermission_NotPresent;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Returns with the physical address of the conflicting cache line
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
Address CacheMemory<ENTRY>::cacheProbe(const Address& address) const
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
assert(!cacheAvail(address));
|
|
|
|
|
|
|
|
Index cacheSet = addressToCacheSet(address);
|
|
|
|
return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)].m_Address;
|
|
|
|
}
|
|
|
|
|
|
|
|
// looks an address up in the cache
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
ENTRY& CacheMemory<ENTRY>::lookup(const Address& address)
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
Index cacheSet = addressToCacheSet(address);
|
|
|
|
int loc = findTagInSet(cacheSet, address);
|
|
|
|
assert(loc != -1);
|
|
|
|
return m_cache[cacheSet][loc];
|
|
|
|
}
|
|
|
|
|
|
|
|
// looks an address up in the cache
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
const ENTRY& CacheMemory<ENTRY>::lookup(const Address& address) const
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
Index cacheSet = addressToCacheSet(address);
|
|
|
|
int loc = findTagInSet(cacheSet, address);
|
|
|
|
assert(loc != -1);
|
|
|
|
return m_cache[cacheSet][loc];
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
AccessPermission CacheMemory<ENTRY>::getPermission(const Address& address) const
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
return lookup(address).m_Permission;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
|
|
|
|
{
|
|
|
|
assert(address == line_address(address));
|
|
|
|
lookup(address).m_Permission = new_perm;
|
|
|
|
assert(getPermission(address) == new_perm);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Sets the most recently used bit for a cache block
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::setMRU(const Address& address)
|
|
|
|
{
|
|
|
|
Index cacheSet;
|
|
|
|
|
|
|
|
cacheSet = addressToCacheSet(address);
|
|
|
|
m_replacementPolicy_ptr->touch(cacheSet,
|
|
|
|
findTagInSet(cacheSet, address),
|
|
|
|
g_eventQueue_ptr->getTime());
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::recordCacheContents(CacheRecorder& tr) const
|
|
|
|
{
|
|
|
|
for (int i = 0; i < m_cache_num_sets; i++) {
|
|
|
|
for (int j = 0; j < m_cache_assoc; j++) {
|
|
|
|
AccessPermission perm = m_cache[i][j].m_Permission;
|
|
|
|
CacheRequestType request_type = CacheRequestType_NULL;
|
|
|
|
if (perm == AccessPermission_Read_Only) {
|
|
|
|
if (m_is_instruction_cache) {
|
|
|
|
request_type = CacheRequestType_IFETCH;
|
|
|
|
} else {
|
|
|
|
request_type = CacheRequestType_LD;
|
|
|
|
}
|
|
|
|
} else if (perm == AccessPermission_Read_Write) {
|
|
|
|
request_type = CacheRequestType_ST;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (request_type != CacheRequestType_NULL) {
|
|
|
|
tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
|
|
|
|
Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::print(ostream& out) const
|
|
|
|
{
|
|
|
|
out << "Cache dump: " << m_description << endl;
|
|
|
|
for (int i = 0; i < m_cache_num_sets; i++) {
|
|
|
|
for (int j = 0; j < m_cache_assoc; j++) {
|
|
|
|
out << " Index: " << i
|
|
|
|
<< " way: " << j
|
|
|
|
<< " entry: " << m_cache[i][j] << endl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
inline
|
|
|
|
void CacheMemory<ENTRY>::printData(ostream& out) const
|
|
|
|
{
|
|
|
|
out << "printData() not supported" << endl;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
void CacheMemory<ENTRY>::getMemoryValue(const Address& addr, char* value,
|
|
|
|
unsigned int size_in_bytes ){
|
|
|
|
ENTRY entry = lookup(line_address(addr));
|
|
|
|
unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
|
|
|
|
for(unsigned int i=0; i<size_in_bytes; ++i){
|
|
|
|
value[i] = entry.m_DataBlk.getByte(i + startByte);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template<class ENTRY>
|
|
|
|
void CacheMemory<ENTRY>::setMemoryValue(const Address& addr, char* value,
|
|
|
|
unsigned int size_in_bytes ){
|
|
|
|
ENTRY& entry = lookup(line_address(addr));
|
|
|
|
unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
|
|
|
|
assert(size_in_bytes > 0);
|
|
|
|
for(unsigned int i=0; i<size_in_bytes; ++i){
|
|
|
|
entry.m_DataBlk.setByte(i + startByte, value[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
entry = lookup(line_address(addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif //CACHEMEMORY_H
|
|
|
|
|