2012-05-23 15:15:45 +02:00
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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*/
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#ifndef __DEV_DMA_DEVICE_HH__
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#define __DEV_DMA_DEVICE_HH__
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2012-08-22 17:40:01 +02:00
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#include <deque>
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2012-05-23 15:15:45 +02:00
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#include "dev/io_device.hh"
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#include "params/DmaDevice.hh"
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class DmaPort : public MasterPort
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{
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2012-10-23 10:49:33 +02:00
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private:
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/**
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* Take the first packet of the transmit list and attempt to send
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* it as a timing request. If it is successful, schedule the
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* sending of the next packet, otherwise remember that we are
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* waiting for a retry.
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*/
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void trySendTimingReq();
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/**
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* For timing, attempt to send the first item on the transmit
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* list, and if it is successful and there are more packets
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* waiting, then schedule the sending of the next packet. For
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* atomic, simply send and process everything on the transmit
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* list.
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*/
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void sendDma();
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/**
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* Handle a response packet by updating the corresponding DMA
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* request state to reflect the bytes received, and also update
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* the pending request counter. If the DMA request that this
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* packet is part of is complete, then signal the completion event
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* if present, potentially with a delay added to it.
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*
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* @param pkt Response packet to handler
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* @param delay Additional delay for scheduling the completion event
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*/
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void handleResp(PacketPtr pkt, Tick delay = 0);
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2012-06-05 07:23:08 +02:00
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struct DmaReqState : public Packet::SenderState
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2012-05-23 15:15:45 +02:00
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{
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/** Event to call on the device when this transaction (all packets)
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* complete. */
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Event *completionEvent;
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/** Total number of bytes that this transaction involves. */
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2012-10-23 10:49:33 +02:00
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const Addr totBytes;
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2012-05-23 15:15:45 +02:00
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/** Number of bytes that have been acked for this transaction. */
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Addr numBytes;
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/** Amount to delay completion of dma by */
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2012-10-23 10:49:33 +02:00
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const Tick delay;
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2012-05-23 15:15:45 +02:00
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DmaReqState(Event *ce, Addr tb, Tick _delay)
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: completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
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{}
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};
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2012-10-23 10:49:33 +02:00
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/** The device that owns this port. */
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2012-05-23 15:15:45 +02:00
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MemObject *device;
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2012-08-22 17:40:01 +02:00
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2012-10-23 10:49:33 +02:00
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/** Use a deque as we never do any insertion or removal in the middle */
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2012-08-22 17:40:01 +02:00
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std::deque<PacketPtr> transmitList;
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2012-05-23 15:15:45 +02:00
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2012-10-23 10:49:33 +02:00
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/** Event used to schedule a future sending from the transmit list. */
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EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
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2012-05-23 15:15:45 +02:00
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/** The system that device/port are in. This is used to select which mode
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* we are currently operating in. */
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System *sys;
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/** Id for all requests */
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2012-10-23 10:49:33 +02:00
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const MasterID masterId;
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2012-05-23 15:15:45 +02:00
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/** Number of outstanding packets the dma port has. */
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2012-08-22 17:40:01 +02:00
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uint32_t pendingCount;
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2012-05-23 15:15:45 +02:00
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/** If we need to drain, keep the drain event around until we're done
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* here.*/
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Event *drainEvent;
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2012-08-22 17:40:01 +02:00
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/** If the port is currently waiting for a retry before it can
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* send whatever it is that it's sending. */
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2012-05-23 15:15:45 +02:00
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bool inRetry;
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2012-10-23 10:49:33 +02:00
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protected:
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2012-08-22 17:40:01 +02:00
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bool recvTimingResp(PacketPtr pkt);
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void recvRetry() ;
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void queueDma(PacketPtr pkt);
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2012-05-23 15:15:45 +02:00
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public:
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2012-08-22 17:39:59 +02:00
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DmaPort(MemObject *dev, System *s);
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2012-05-23 15:15:45 +02:00
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void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data, Tick delay, Request::Flags flag = 0);
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2012-08-22 17:40:01 +02:00
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bool dmaPending() const { return pendingCount > 0; }
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2012-05-23 15:15:45 +02:00
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unsigned cacheBlockSize() const { return peerBlockSize(); }
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unsigned int drain(Event *de);
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};
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class DmaDevice : public PioDevice
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{
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protected:
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DmaPort dmaPort;
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public:
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typedef DmaDeviceParams Params;
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DmaDevice(const Params *p);
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2012-08-22 17:40:01 +02:00
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virtual ~DmaDevice() { }
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2012-05-23 15:15:45 +02:00
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void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
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Tick delay = 0)
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{
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dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
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}
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void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
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Tick delay = 0)
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{
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dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
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}
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2012-10-23 10:49:33 +02:00
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bool dmaPending() const { return dmaPort.dmaPending(); }
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2012-05-23 15:15:45 +02:00
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virtual void init();
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virtual unsigned int drain(Event *de);
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unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
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2012-10-15 14:12:35 +02:00
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virtual BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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2012-05-23 15:15:45 +02:00
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};
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#endif // __DEV_DMA_DEVICE_HH__
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