488 lines
54 KiB
Text
488 lines
54 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 165173 # Simulator instruction rate (inst/s)
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host_mem_usage 251872 # Number of bytes of host memory used
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host_seconds 10349.18 # Real time elapsed on the host
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host_tick_rate 71148819 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1709408682 # Number of instructions simulated
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sim_seconds 0.736332 # Number of seconds simulated
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sim_ticks 736332221500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 251161589 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 289953961 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 20139757 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 310539803 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 310539803 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 203576342 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 42336019 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 1325593863 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.289542 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.917523 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 632760901 47.73% 47.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 317626873 23.96% 71.70% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 153247647 11.56% 83.26% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 83932703 6.33% 89.59% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 35877325 2.71% 92.29% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 27102905 2.04% 94.34% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 13190001 1.00% 95.33% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 19519489 1.47% 96.81% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 42336019 3.19% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1709408682 # Number of instructions committed
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system.cpu.commit.COM:loads 485926830 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 660773875 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 33291323 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1709408682 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 333 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 724671522 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1709408682 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1709408682 # Number of Instructions Simulated
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system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 535355954 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14975.678248 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11475.231071 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 527355564 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 119811266500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.014944 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 8000390 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 345154 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 87845602000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.014299 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7655236 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23783.327584 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20862.502653 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 168018197 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 108640123688 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.026467 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 4567911 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 2675787 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 39474441969 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1892124 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 3127.917167 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 72.834141 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 25171 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 78732803 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 707942062 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 18176.791771 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 695373761 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 228451390188 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.017753 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 12568301 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 3020941 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 127320043969 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.013486 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9547360 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.997284 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4084.873750 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 707942062 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 18176.791771 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 695373761 # number of overall hits
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system.cpu.dcache.overall_miss_latency 228451390188 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.017753 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 12568301 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 3020941 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 127320043969 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.013486 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9547360 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 9543264 # number of replacements
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system.cpu.dcache.sampled_refs 9547360 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4084.873750 # Cycle average of tags in use
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system.cpu.dcache.total_refs 695373761 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 7250730000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 3122652 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 107521017 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 2640561192 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 660508331 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 547645494 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 111598676 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 9919021 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 310539803 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 305341372 # Number of cache lines fetched
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system.cpu.fetch.Cycles 575112901 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 5844114 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2356609774 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 3056047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 35765564 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.210869 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 305341372 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 251161589 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.600235 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1437192539 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.882507 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.825084 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 863142869 60.06% 60.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 76123612 5.30% 65.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 84397778 5.87% 71.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 62407182 4.34% 75.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 54486198 3.79% 79.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 66150908 4.60% 83.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 49722936 3.46% 87.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 19741369 1.37% 88.80% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 161019687 11.20% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 305340411 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 32807500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 961 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 215 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 25509000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 409303.500000 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 305341372 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 34138.917794 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
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system.cpu.icache.demand_hits 305340411 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 32807500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_misses 961 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 215 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 25509000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.297244 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 608.756375 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 305341372 # number of overall (read+write) accesses
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||
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|
system.cpu.icache.overall_avg_miss_latency 34138.917794 # average overall miss latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||
|
|
system.cpu.icache.overall_hits 305340411 # number of overall hits
|
||
|
|
system.cpu.icache.overall_miss_latency 32807500 # number of overall miss cycles
|
||
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||
|
|
system.cpu.icache.overall_misses 961 # number of overall misses
|
||
|
|
system.cpu.icache.overall_mshr_hits 215 # number of overall MSHR hits
|
||
|
|
system.cpu.icache.overall_mshr_miss_latency 25509000 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
|
||
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||
|
|
system.cpu.icache.replacements 10 # number of replacements
|
||
|
|
system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||
|
|
system.cpu.icache.tagsinuse 608.756375 # Cycle average of tags in use
|
||
|
|
system.cpu.icache.total_refs 305340411 # Total number of references to valid blocks.
|
||
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||
|
|
system.cpu.idleCycles 35471905 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||
|
|
system.cpu.iew.EXEC:branches 234624640 # Number of branches executed
|
||
|
|
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||
|
|
system.cpu.iew.EXEC:rate 1.389966 # Inst execution rate
|
||
|
|
system.cpu.iew.EXEC:refs 783869507 # number of memory reference insts executed
|
||
|
|
system.cpu.iew.EXEC:stores 215578815 # Number of stores executed
|
||
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||
|
|
system.cpu.iew.WB:consumers 2289056926 # num instructions consuming a value
|
||
|
|
system.cpu.iew.WB:count 2009251521 # cumulative count of insts written-back
|
||
|
|
system.cpu.iew.WB:fanout 0.549566 # average fanout of values written-back
|
||
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||
|
|
system.cpu.iew.WB:producers 1257988693 # num instructions producing a value
|
||
|
|
system.cpu.iew.WB:rate 1.364365 # insts written-back per cycle
|
||
|
|
system.cpu.iew.WB:sent 2020755883 # cumulative count of insts sent to commit
|
||
|
|
system.cpu.iew.branchMispredicts 34959273 # Number of branch mispredicts detected at execute
|
||
|
|
system.cpu.iew.iewBlockCycles 18898435 # Number of cycles IEW is blocking
|
||
|
|
system.cpu.iew.iewDispLoadInsts 660629203 # Number of dispatched load instructions
|
||
|
|
system.cpu.iew.iewDispNonSpecInsts 422 # Number of dispatched non-speculative instructions
|
||
|
|
system.cpu.iew.iewDispSquashedInsts 10495423 # Number of squashed instructions skipped by dispatch
|
||
|
|
system.cpu.iew.iewDispStoreInsts 320206682 # Number of dispatched store instructions
|
||
|
|
system.cpu.iew.iewDispatchedInsts 2433961539 # Number of instructions dispatched to IQ
|
||
|
|
system.cpu.iew.iewExecLoadInsts 568290692 # Number of load instructions executed
|
||
|
|
system.cpu.iew.iewExecSquashedInsts 53852412 # Number of squashed instructions skipped in execute
|
||
|
|
system.cpu.iew.iewExecutedInsts 2046953136 # Number of executed instructions
|
||
|
|
system.cpu.iew.iewIQFullEvents 1105294 # Number of times the IQ has become full, causing a stall
|
||
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||
|
|
system.cpu.iew.iewLSQFullEvents 81032 # Number of times the LSQ has become full, causing a stall
|
||
|
|
system.cpu.iew.iewSquashCycles 111598676 # Number of cycles IEW is squashing
|
||
|
|
system.cpu.iew.iewUnblockCycles 1881770 # Number of cycles IEW is unblocking
|
||
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 185278 # Number of times an access to memory failed due to the cache being blocked
|
||
|
|
system.cpu.iew.lsq.thread.0.forwLoads 29166049 # Number of loads that had data forwarded from stores
|
||
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 474578 # Number of memory responses ignored because the instruction is squashed
|
||
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 2909115 # Number of memory ordering violations
|
||
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 174702372 # Number of loads squashed
|
||
|
|
system.cpu.iew.lsq.thread.0.squashedStores 145359637 # Number of stores squashed
|
||
|
|
system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations
|
||
|
|
system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly
|
||
|
|
system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly
|
||
|
|
system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle
|
||
|
|
system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1282325001 61.04% 61.04% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1250884 0.06% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 20 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 3 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 17 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.10% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 577865457 27.51% 88.61% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 239364164 11.39% 100.00% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:FU_type_0::total 2100805548 # Type of FU issued
|
||
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 35252464 # FU busy when requested
|
||
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.016780 # FU busy rate (busy events/executed inst)
|
||
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 38199 0.11% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 25515421 72.38% 72.49% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 9698844 27.51% 100.00% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1437192539 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.461743 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.631414 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 547476469 38.09% 38.09% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 329329940 22.91% 61.01% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 229433093 15.96% 76.97% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 157481559 10.96% 87.93% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 82220449 5.72% 93.65% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 49053587 3.41% 97.06% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 31255179 2.17% 99.24% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 9054164 0.63% 99.87% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 1888099 0.13% 100.00% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle
|
||
|
|
system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate
|
||
|
|
system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec)
|
||
|
|
system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued
|
||
|
|
system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ
|
||
|
|
system.cpu.iq.iqSquashedInstsExamined 717692858 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||
|
|
system.cpu.iq.iqSquashedInstsIssued 28325044 # Number of squashed instructions issued
|
||
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed
|
||
|
|
system.cpu.iq.iqSquashedOperandsExamined 1287267033 # Number of squashed operands that are examined and possibly removed from graph
|
||
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
||
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||
|
|
system.cpu.itb.hits 0 # DTB hits
|
||
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||
|
|
system.cpu.itb.misses 0 # DTB misses
|
||
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.l2cache.ReadExReq_accesses 1892128 # number of ReadExReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34475.157161 # average ReadExReq miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31331.098502 # average ReadExReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_hits 979531 # number of ReadExReq hits
|
||
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31461925000 # number of ReadExReq miss cycles
|
||
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482313 # miss rate for ReadExReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_misses 912597 # number of ReadExReq misses
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28592666500 # number of ReadExReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482313 # mshr miss rate for ReadExReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912597 # number of ReadExReq MSHR misses
|
||
|
|
system.cpu.l2cache.ReadReq_accesses 7655978 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34344.776594 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31123.973478 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_hits 5633361 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.ReadReq_miss_latency 69466329000 # number of ReadReq miss cycles
|
||
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.264188 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_misses 2022617 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 62951535500 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264186 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2022606 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.l2cache.Writeback_accesses 3122652 # number of Writeback accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.Writeback_hits 3122652 # number of Writeback hits
|
||
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3948.352875 # average number of cycles each access was blocked
|
||
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||
|
|
system.cpu.l2cache.avg_refs 2.651904 # Average number of references to valid blocks.
|
||
|
|
system.cpu.l2cache.blocked::no_mshrs 3582 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 14143000 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||
|
|
system.cpu.l2cache.demand_accesses 9548106 # number of demand (read+write) accesses
|
||
|
|
system.cpu.l2cache.demand_avg_miss_latency 34385.313643 # average overall miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_hits 6612892 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.demand_miss_latency 100928254000 # number of demand (read+write) miss cycles
|
||
|
|
system.cpu.l2cache.demand_miss_rate 0.307413 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_misses 2935214 # number of demand (read+write) misses
|
||
|
|
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
||
|
|
system.cpu.l2cache.demand_mshr_miss_latency 91544202000 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307412 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_mshr_misses 2935203 # number of demand (read+write) MSHR misses
|
||
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
|
system.cpu.l2cache.occ_%::0 0.494634 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.occ_%::1 0.321250 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.occ_blocks::0 16208.167153 # Average occupied blocks per context
|
||
|
|
system.cpu.l2cache.occ_blocks::1 10526.735069 # Average occupied blocks per context
|
||
|
|
system.cpu.l2cache.overall_accesses 9548106 # number of overall (read+write) accesses
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency 34385.313643 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.overall_hits 6612892 # number of overall hits
|
||
|
|
system.cpu.l2cache.overall_miss_latency 100928254000 # number of overall miss cycles
|
||
|
|
system.cpu.l2cache.overall_miss_rate 0.307413 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_misses 2935214 # number of overall misses
|
||
|
|
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_latency 91544202000 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307412 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_misses 2935203 # number of overall MSHR misses
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||
|
|
system.cpu.l2cache.replacements 2922772 # number of replacements
|
||
|
|
system.cpu.l2cache.sampled_refs 2950094 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||
|
|
system.cpu.l2cache.tagsinuse 26734.902222 # Cycle average of tags in use
|
||
|
|
system.cpu.l2cache.total_refs 7823366 # Total number of references to valid blocks.
|
||
|
|
system.cpu.l2cache.warmup_cycle 156475359000 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.l2cache.writebacks 1217059 # number of writebacks
|
||
|
|
system.cpu.memDep0.conflictingLoads 102861524 # Number of conflicting loads.
|
||
|
|
system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores.
|
||
|
|
system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit.
|
||
|
|
system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit.
|
||
|
|
system.cpu.numCycles 1472664444 # number of cpu cycles simulated
|
||
|
|
system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking
|
||
|
|
system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed
|
||
|
|
system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full
|
||
|
|
system.cpu.rename.RENAME:IdleCycles 691140909 # Number of cycles rename is idle
|
||
|
|
system.cpu.rename.RENAME:LSQFullEvents 38063722 # Number of times rename has blocked due to LSQ full
|
||
|
|
system.cpu.rename.RENAME:ROBFullEvents 9972 # Number of times rename has blocked due to ROB full
|
||
|
|
system.cpu.rename.RENAME:RenameLookups 7136669468 # Number of register rename lookups that rename has made
|
||
|
|
system.cpu.rename.RENAME:RenamedInsts 2563712800 # Number of instructions processed by rename
|
||
|
|
system.cpu.rename.RENAME:RenamedOperands 1945900239 # Number of destination operands rename has renamed
|
||
|
|
system.cpu.rename.RENAME:RunCycles 526018927 # Number of cycles rename is running
|
||
|
|
system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing
|
||
|
|
system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking
|
||
|
|
system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing
|
||
|
|
system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst
|
||
|
|
system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed
|
||
|
|
system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer
|
||
|
|
system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed
|
||
|
|
system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||
|
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||
|
|
|
||
|
|
---------- End Simulation Statistics ----------
|