2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2010-09-09 20:40:19 +02:00
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host_inst_rate 898977 # Simulator instruction rate (inst/s)
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host_mem_usage 219380 # Number of bytes of host memory used
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host_seconds 383.10 # Real time elapsed on the host
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host_tick_rate 1372552338 # Simulator tick rate (ticks/s)
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2010-07-27 07:03:44 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2010-08-26 02:10:42 +02:00
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sim_insts 344399678 # Number of instructions simulated
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2010-09-09 20:40:19 +02:00
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sim_seconds 0.525828 # Number of seconds simulated
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sim_ticks 525827779000 # Number of ticks simulated
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 94585118 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 79912000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1607 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 82060677 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 162078000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2895 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 153393000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 2895 # number of WriteReq MSHR misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_avg_miss_latency 53751.665926 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 176645795 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 241990000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4502 # number of demand (read+write) misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 228484000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 4502 # number of demand (read+write) MSHR misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 3079.430321 # Average occupied blocks per context
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.overall_avg_miss_latency 53751.665926 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.overall_hits 176645795 # number of overall hits
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system.cpu.dcache.overall_miss_latency 241990000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4502 # number of overall misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 228484000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 4502 # number of overall MSHR misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1332 # number of replacements
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system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.tagsinuse 3079.430321 # Cycle average of tags in use
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2010-07-27 07:03:44 +02:00
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system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 974 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 348627536 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 348611933 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 22342.622124 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 348627536 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
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system.cpu.icache.demand_hits 348611933 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses
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system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-09-09 20:40:19 +02:00
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system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 1766.000778 # Average occupied blocks per context
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 348611933 # number of overall hits
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system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses
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system.cpu.icache.overall_misses 15603 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 13796 # number of replacements
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system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-09-09 20:40:19 +02:00
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system.cpu.icache.tagsinuse 1766.000778 # Cycle average of tags in use
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_miss_latency 149292000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 0.999652 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 2871 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 114840000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999652 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 2871 # number of ReadExReq MSHR misses
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 13233 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.231087 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
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|
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.UpgradeReq_miss_latency 1196000 # number of UpgradeReq miss cycles
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 920000 # number of UpgradeReq MSHR miss cycles
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2010-09-09 20:40:19 +02:00
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system.cpu.l2cache.avg_refs 2.717391 # Average number of references to valid blocks.
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2010-07-27 07:03:44 +02:00
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.demand_hits 13234 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 356096000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.341002 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 6848 # number of demand (read+write) misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 273920000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.341002 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 6848 # number of demand (read+write) MSHR misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.010365 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 3134.105136 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 339.639233 # Average occupied blocks per context
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.overall_hits 13234 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 356096000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.341002 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 6848 # number of overall misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 273920000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.341002 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 6848 # number of overall MSHR misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 48 # number of replacements
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 4876 # Sample count of references to valid blocks.
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 3473.744369 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 13250 # Total number of references to valid blocks.
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.numCycles 1051655558 # number of cpu cycles simulated
|
2010-08-26 02:10:42 +02:00
|
|
|
system.cpu.num_insts 344399678 # Number of instructions executed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.num_refs 177028576 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
