240 lines
8.7 KiB
C++
240 lines
8.7 KiB
C++
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#include "model/electrical/OR.h"
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#include <cmath>
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#include "model/PortInfo.h"
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#include "model/TransitionInfo.h"
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#include "model/EventInfo.h"
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#include "model/std_cells/StdCellLib.h"
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#include "model/std_cells/StdCell.h"
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#include "model/timing_graph/ElectricalNet.h"
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namespace DSENT
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{
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using std::ceil;
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using std::floor;
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OR::OR(const String& instance_name_, const TechModel* tech_model_)
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: ElectricalModel(instance_name_, tech_model_)
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{
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initParameters();
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initProperties();
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}
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OR::~OR()
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{}
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void OR::initParameters()
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{
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addParameterName("NumberInputs");
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addParameterName("NumberBits");
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addParameterName("BitDuplicate", "TRUE");
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return;
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}
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void OR::initProperties()
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{
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return;
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}
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OR* OR::clone() const
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{
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// TODO
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return NULL;
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}
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void OR::constructModel()
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{
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// Get parameter
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unsigned int number_inputs = getParameter("NumberInputs").toUInt();
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unsigned int number_bits = getParameter("NumberBits").toUInt();
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bool bit_duplicate = getParameter("BitDuplicate").toBool();
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ASSERT(number_inputs > 0, "[Error] " + getInstanceName() +
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" -> Number of inputs must be > 0!");
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ASSERT(number_bits > 0, "[Error] " + getInstanceName() +
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" -> Number of bits must be > 0!");
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// Init ports
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for(unsigned int i = 0; i < number_inputs; ++i)
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{
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createInputPort("In" + (String)i, makeNetIndex(0, number_bits-1));
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}
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createOutputPort("Out", makeNetIndex(0, number_bits-1));
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// Number of inputs on the 0 side
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unsigned int or0_number_inputs = (unsigned int)ceil((double)number_inputs / 2.0);
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// Number of inputs on the 1 side
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unsigned int or1_number_inputs = (unsigned int)floor((double)number_inputs / 2.0);
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// Create area, power, and event results
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createElectricalResults();
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createElectricalEventResult("OR");
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getEventInfo("Idle")->setStaticTransitionInfos();
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//Depending on whether we want to create a 1-bit instance and have it multiplied
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//up by number of bits or actually instantiate number_bits of 1-bit instances.
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//Recursively instantiates smaller ors
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if(bit_duplicate || number_bits == 1)
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{
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// If it is just a 1-input or, just connect output to input
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if(number_inputs == 1)
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{
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assign("Out", "In0");
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}
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else
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{
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// If it is more than 1 input, instantiate two sub ors (OR_way0 and OR_way1)
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// and create a final OR2 to OR them
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const String& or0_name = "OR_way0";
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const String& or1_name = "OR_way1";
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const String& orf_name = "OR2_i" + (String)number_inputs;
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OR* or0 = new OR(or0_name, getTechModel());
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or0->setParameter("NumberInputs", or0_number_inputs);
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or0->setParameter("NumberBits", 1);
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or0->setParameter("BitDuplicate", "TRUE");
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or0->construct();
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OR* or1 = new OR(or1_name, getTechModel());
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or1->setParameter("NumberInputs", or1_number_inputs);
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or1->setParameter("NumberBits", 1);
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or1->setParameter("BitDuplicate", "TRUE");
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or1->construct();
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StdCell* orf = getTechModel()->getStdCellLib()->createStdCell("OR2", orf_name);
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orf->construct();
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// Create outputs of way0 and way1 ors with final or
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createNet("way0_Out");
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createNet("way1_Out");
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portConnect(or0, "Out", "way0_Out");
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portConnect(or1, "Out", "way1_Out");
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portConnect(orf, "A", "way0_Out");
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portConnect(orf, "B", "way1_Out");
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// Connect inputs to the sub ors.
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for(unsigned int i = 0; i < or0_number_inputs; ++i)
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{
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createNet("way0_In" + (String)i);
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portConnect(or0, "In" + (String)i, "way0_In" + (String)i);
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assignVirtualFanin("way0_In" + (String)i, "In" + (String)i);
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}
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for(unsigned int i = 0; i < or1_number_inputs; ++i)
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{
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createNet("way1_In" + (String)i);
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portConnect(or1, "In" + (String)i, "way1_In" + (String)i);
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assignVirtualFanin("way1_In" + (String)i, "In" + (String)(i + or0_number_inputs));
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}
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// Connect outputs
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createNet("OR2_Out");
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portConnect(orf, "Y", "OR2_Out");
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assignVirtualFanout("Out", "OR2_Out");
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addSubInstances(or0, number_bits);
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addElectricalSubResults(or0, number_bits);
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addSubInstances(or1, number_bits);
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addElectricalSubResults(or1, number_bits);
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addSubInstances(orf, number_bits);
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addElectricalSubResults(orf, number_bits);
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Result* or_event = getEventResult("OR");
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or_event->addSubResult(or0->getEventResult("OR"), or0_name, number_bits);
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or_event->addSubResult(or1->getEventResult("OR"), or1_name, number_bits);
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or_event->addSubResult(orf->getEventResult("OR2"), orf_name, number_bits);
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}
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}
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else
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{
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// Init a bunch of 1-bit ors
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Result* or_event = getEventResult("OR");
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for(unsigned int n = 0; n < number_bits; ++n)
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{
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const String& or_name = "OR_bit" + (String)n;
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OR* ors = new OR(or_name, getTechModel());
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ors->setParameter("NumberInputs", number_inputs);
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ors->setParameter("NumberBits", 1);
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ors->setParameter("BitDuplicate", "TRUE");
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ors->construct();
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for(unsigned int i = 0; i < number_inputs; ++i)
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{
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portConnect(ors, "In" + (String)i, "In" + (String)i, makeNetIndex(n));
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}
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portConnect(ors, "Out", "Out", makeNetIndex(n));
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addSubInstances(ors, 1.0);
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addElectricalSubResults(ors, 1.0);
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or_event->addSubResult(ors->getEventResult("OR"), or_name, 1.0);
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}
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}
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return;
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}
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void OR::propagateTransitionInfo()
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{
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// Get parameters
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unsigned int number_inputs = getParameter("NumberInputs").toUInt();
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unsigned int number_bits = getParameter("NumberBits").toUInt();
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bool bit_duplicate = getParameter("BitDuplicate").toBool();
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// Number of inputs on 0 side
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unsigned int or0_number_inputs = (unsigned int)ceil((double)number_inputs / 2.0);
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unsigned int or1_number_inputs = (unsigned int)floor((double)number_inputs / 2.0);
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if(bit_duplicate || number_bits == 1)
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{
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if(number_inputs == 1)
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{
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propagatePortTransitionInfo("Out", "In0");
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}
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else
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{
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ElectricalModel* or0 = (ElectricalModel*)getSubInstance("OR_way0");
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for(unsigned int i = 0; i < or0_number_inputs; ++i)
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{
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propagatePortTransitionInfo(or0, "In" + (String)i, "In" + (String)i);
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}
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or0->use();
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ElectricalModel* or1 = (ElectricalModel*)getSubInstance("OR_way1");
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for(unsigned int i = 0; i < or1_number_inputs; ++i)
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{
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propagatePortTransitionInfo(or1, "In" + (String)i, "In" + (String)i);
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}
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or1->use();
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ElectricalModel* orf = (ElectricalModel*)getSubInstance("OR2_i" + (String)number_inputs);
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propagatePortTransitionInfo(orf, "A", or0, "Out");
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propagatePortTransitionInfo(orf, "B", or1, "Out");
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orf->use();
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// Set output probability
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propagatePortTransitionInfo("Out", orf, "Y");
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}
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}
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else
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{
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for(unsigned int n = 0; n < number_bits; ++n)
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{
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ElectricalModel* or_bit = (ElectricalModel*)getSubInstance("OR_bit" + (String)n);
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for(unsigned int i = 0; i < number_inputs; ++i)
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{
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propagatePortTransitionInfo(or_bit, "In" + (String)i, "In" + (String)i);
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}
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or_bit->use();
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}
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ElectricalModel* or_bit = (ElectricalModel*)getSubInstance("OR_bit0");
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propagatePortTransitionInfo("Out", or_bit, "Out");
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}
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return;
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}
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} // namespace DSENT
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