227 lines
10 KiB
C++
227 lines
10 KiB
C++
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#include "model/electrical/MuxTreeSerializer.h"
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#include <cmath>
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#include "model/PortInfo.h"
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#include "model/TransitionInfo.h"
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#include "model/EventInfo.h"
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#include "model/std_cells/StdCellLib.h"
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#include "model/std_cells/StdCell.h"
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#include "model/electrical/Multiplexer.h"
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#include "model/timing_graph/ElectricalNet.h"
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namespace DSENT
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{
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using std::ceil;
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MuxTreeSerializer::MuxTreeSerializer(const String& instance_name_, const TechModel* tech_model_)
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: ElectricalModel(instance_name_, tech_model_)
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{
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initParameters();
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initProperties();
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}
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MuxTreeSerializer::~MuxTreeSerializer()
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{}
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void MuxTreeSerializer::initParameters()
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{
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addParameterName("InDataRate");
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addParameterName("OutDataRate");
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addParameterName("InBits"); //Output width will just be input width / serialization ratio
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}
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void MuxTreeSerializer::initProperties()
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{
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return;
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}
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MuxTreeSerializer* MuxTreeSerializer::clone() const
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{
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// TODO
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return NULL;
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}
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void MuxTreeSerializer::constructModel()
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{
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// Get parameters
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double in_data_rate = getParameter("InDataRate").toDouble();
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double out_data_rate = getParameter("OutDataRate").toDouble();
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unsigned int in_bits = getParameter("InBits").toUInt();
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// Calculate serialization ratio
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unsigned int serialization_ratio = (unsigned int) floor(out_data_rate / in_data_rate);
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ASSERT(serialization_ratio == out_data_rate / in_data_rate,
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"[Error] " + getInstanceName() + " -> Cannot have non-integer serialization ratios " +
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"(" + (String) (in_data_rate / out_data_rate) + ")!");
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// Calculate output width
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ASSERT(floor((double) in_bits / serialization_ratio) == (double) in_bits / serialization_ratio,
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"[Error] " + getInstanceName() + " -> Input width (" + (String) in_bits + ") " +
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"must be a multiple of the serialization ratio (" + (String) serialization_ratio + ")!");
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unsigned int output_bits = in_bits / serialization_ratio;
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// Calculate the number of multiplexer stages
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unsigned int number_stages = (unsigned int)ceil(log2((double) serialization_ratio));
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// Store calculated values
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getGenProperties()->set("SerializationRatio", serialization_ratio);
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getGenProperties()->set("OutputBits", output_bits);
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getGenProperties()->set("NumberStages", number_stages);
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// Create ports
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createInputPort("In", makeNetIndex(0, in_bits-1));
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createInputPort("OutCK");
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createOutputPort("Out", makeNetIndex(0, output_bits-1));
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//Create energy, power, and area results
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createElectricalResults();
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createElectricalEventResult("Serialize");
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getEventInfo("Serialize")->setTransitionInfo("OutCK", TransitionInfo(0.0, (double) serialization_ratio / 2.0, 0.0));
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//Set conditions during idle state
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getEventInfo("Idle")->setStaticTransitionInfos();
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getEventInfo("Idle")->setTransitionInfo("OutCK", TransitionInfo(0.0, (double) serialization_ratio / 2.0, 0.0));
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// Mark OutCK as a false path (since timing tool will do strange stuff due to all the clock divides and stuff)
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getNet("OutCK")->setFalsePath(true);
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// Create mux-tree instance
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if (serialization_ratio == 1)
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{
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// No need to do anything, hohoho
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assign("Out", "In");
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}
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else
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{
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// Create multiplexer
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String mux_tree_name = "MuxTree";
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ElectricalModel* mux_tree = new Multiplexer(mux_tree_name, getTechModel());
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mux_tree->setParameter("NumberInputs", serialization_ratio);
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mux_tree->setParameter("NumberBits", output_bits);
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mux_tree->setParameter("BitDuplicate", "TRUE");
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mux_tree->construct();
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// Create nets
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if (number_stages > 1)
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createNet("MuxSel_b", makeNetIndex(0, number_stages-2));
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createNet("MuxSel", makeNetIndex(0, number_stages-1));
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assign("MuxSel", makeNetIndex(number_stages-1), "OutCK");
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// Create reindexed net (to help out with indexing)
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createNet("InTmp", makeNetIndex(0, in_bits-1));
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for (unsigned int i = 0; i < serialization_ratio; ++i)
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for (unsigned int j = 0; j < output_bits; ++j)
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assign("InTmp", makeNetIndex(i*output_bits+j), "In", makeNetIndex(j*serialization_ratio+i));
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// Connect ports
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for (unsigned int i = 0; i < serialization_ratio; ++i)
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portConnect(mux_tree, "In" + (String) i, "InTmp", makeNetIndex(i*output_bits, (i+1)*output_bits-1));
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for (unsigned int i = 0; i < number_stages; ++i)
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portConnect(mux_tree, "Sel" + (String) i, "MuxSel", makeNetIndex(i));
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portConnect(mux_tree, "Out", "Out");
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// Add subinstance and events
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addSubInstances(mux_tree, 1.0);
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addElectricalSubResults(mux_tree, 1.0);
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// Add serialize event/power
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getEventResult("Serialize")->addSubResult(mux_tree->getEventResult("Mux"), mux_tree_name, 1.0);
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// Create clock dividers (assumes power of 2...), don't need divider for fastest output stage
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for (unsigned int i = 0; i < number_stages - 1; ++i)
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{
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// Clk dividing registers
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const String& clk_div_dff_name = "ClkDivDFF_" + (String) i;
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StdCell* clk_div_dff = getTechModel()->getStdCellLib()->createStdCell("DFFQ", clk_div_dff_name);
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clk_div_dff->construct();
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portConnect(clk_div_dff, "D", "MuxSel_b", makeNetIndex(i));
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portConnect(clk_div_dff, "Q", "MuxSel", makeNetIndex(i));
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portConnect(clk_div_dff, "CK", "MuxSel", makeNetIndex(i+1));
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addSubInstances(clk_div_dff, 1.0);
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addElectricalSubResults(clk_div_dff, 1.0);
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// Inversions
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const String& clk_div_inv_name = "ClkDivINV_" + (String) i;
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StdCell* clk_div_inv = getTechModel()->getStdCellLib()->createStdCell("INV", clk_div_inv_name);
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clk_div_inv->construct();
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portConnect(clk_div_inv, "A", "MuxSel", makeNetIndex(i));
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portConnect(clk_div_inv, "Y", "MuxSel_b", makeNetIndex(i));
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addSubInstances(clk_div_inv, 1.0);
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addElectricalSubResults(clk_div_inv, 1.0);
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getEventResult("Serialize")->addSubResult(clk_div_dff->getEventResult("CK"), clk_div_dff_name, 1.0);
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getEventResult("Serialize")->addSubResult(clk_div_dff->getEventResult("DFFD"), clk_div_dff_name, 1.0);
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getEventResult("Serialize")->addSubResult(clk_div_dff->getEventResult("DFFQ"), clk_div_dff_name, 1.0);
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getEventResult("Serialize")->addSubResult(clk_div_inv->getEventResult("INV"), clk_div_inv_name, 1.0);
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}
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}
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return;
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}
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void MuxTreeSerializer::propagateTransitionInfo()
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{
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// Get some generated properties
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const unsigned int serialization_ratio = getGenProperties()->get("SerializationRatio");
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const unsigned int number_stages = getGenProperties()->get("NumberStages");
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// Set transition info of the mux tree and clock divide DFF
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if (serialization_ratio == 1)
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{
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// If no serialization, then just propagate input transition info to output port
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propagatePortTransitionInfo("Out", "In");
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}
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else
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{
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// Propagate transition probabilities to the mux tree
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ElectricalModel* mux_tree = (ElectricalModel*) getSubInstance("MuxTree");
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// All input ports of the mux have the same probability
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for (unsigned int i = 0; i < serialization_ratio; ++i)
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propagatePortTransitionInfo(mux_tree, "In" + (String) i, "In");
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// Connect last stage of the mux
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propagatePortTransitionInfo(mux_tree, "Sel" + (String) (number_stages - 1), "OutCK");
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// Keep track of the last clock divider
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ElectricalModel* last_clk_div_dff = NULL;
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// Find P01 of OutCK
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double last_P01_CK = getInputPort("OutCK")->getTransitionInfo().getNumberTransitions01();
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// Start from the last stage (since it is the stage with no clock division)
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for (unsigned int i = 0; i < number_stages - 1; ++i)
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{
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const String& clk_div_dff_name = "ClkDivDFF_" + (String) (number_stages - i - 2);
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const String& clk_div_inv_name = "ClkDivINV_" + (String) (number_stages - i - 2);
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ElectricalModel* clk_div_dff = (ElectricalModel*) getSubInstance(clk_div_dff_name);
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if (last_clk_div_dff == NULL)
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propagatePortTransitionInfo(clk_div_dff, "CK", "OutCK");
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else
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propagatePortTransitionInfo(clk_div_dff, "CK", last_clk_div_dff, "Q");
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// Since it is a clock divider, P01 is D and Q are simply half the P01 of D and Q of
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// the input clock
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if (last_P01_CK != 0) clk_div_dff->getInputPort("D")->setTransitionInfo(TransitionInfo(0.0, last_P01_CK * 0.5, 0.0));
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else clk_div_dff->getInputPort("D")->setTransitionInfo(TransitionInfo(0.5, 0.0, 0.5));
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clk_div_dff->use();
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ElectricalModel* clk_div_inv = (ElectricalModel*) getSubInstance(clk_div_inv_name);
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propagatePortTransitionInfo(clk_div_inv, "A", clk_div_dff, "Q");
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clk_div_inv->use();
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// Connect select port of the mux
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propagatePortTransitionInfo(mux_tree, "Sel" + (String) (number_stages - i - 2), clk_div_dff, "Q");
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// Clk divide by 2;
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last_P01_CK = last_P01_CK * 0.5;
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// Remember the last clk div DFF
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last_clk_div_dff = clk_div_dff;
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}
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mux_tree->use();
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// Set output transition info to be the output transition info of the mux tree
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propagatePortTransitionInfo("Out", mux_tree, "Out");
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}
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return;
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}
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} // namespace DSENT
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