2009-05-13 07:55:04 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2010-06-25 23:42:55 +02:00
|
|
|
host_inst_rate 22033 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 154168 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.26 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 110232758 # Simulator tick rate (ticks/s)
|
2009-05-13 07:55:04 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2009-12-31 21:30:51 +01:00
|
|
|
sim_insts 5827 # Number of instructions simulated
|
2010-02-01 00:31:28 +01:00
|
|
|
sim_seconds 0.000029 # Number of seconds simulated
|
2010-06-25 23:42:55 +02:00
|
|
|
sim_ticks 29206500 # Number of ticks simulated
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations
|
|
|
|
|
system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage
|
|
|
|
|
system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits
|
|
|
|
|
system.cpu.Branch-Predictor.BTBLookups 160 # Number of BTB lookups
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.Branch-Predictor.RASInCorrect 35 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.Branch-Predictor.condIncorrect 556 # Number of conditional branches incorrect
|
2010-03-23 05:26:53 +01:00
|
|
|
system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.Branch-Predictor.lookups 916 # Number of BP lookups
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.Branch-Predictor.predictedNotTaken 802 # Number of Branches Predicted As Not Taken (False).
|
|
|
|
|
system.cpu.Branch-Predictor.predictedTaken 114 # Number of Branches Predicted As Taken (True).
|
2010-03-23 05:26:53 +01:00
|
|
|
system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target.
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.Execution-Unit.executions 3734 # Number of Instructions Executed.
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.Execution-Unit.mispredictPct 60.698690 # Percentage of Incorrect Branches Predicts
|
|
|
|
|
system.cpu.Execution-Unit.mispredicted 556 # Number of Branches Incorrectly Predicted
|
|
|
|
|
system.cpu.Execution-Unit.predicted 360 # Number of Branches Incorrectly Predicted
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 # Number of Branches Incorrectly Predicted As Not Taken).
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken.
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed
|
|
|
|
|
system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.RegFile-Manager.regFileAccesses 10682 # Number of Total Accesses (Read+Write) to the Register File
|
|
|
|
|
system.cpu.RegFile-Manager.regFileReads 7272 # Number of Reads from Register File
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.RegFile-Manager.regForwards 31 # Number of Registers Read Through Forwarding Logic
|
|
|
|
|
system.cpu.activity 20.277673 # Percentage of cycles cpu is active
|
2010-06-24 00:21:44 +02:00
|
|
|
system.cpu.comBranches 916 # Number of Branches instructions committed
|
|
|
|
|
system.cpu.comFloats 0 # Number of Floating Point instructions committed
|
|
|
|
|
system.cpu.comInts 2155 # Number of Integer instructions committed
|
|
|
|
|
system.cpu.comLoads 1164 # Number of Load instructions committed
|
|
|
|
|
system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
|
|
|
|
|
system.cpu.comNops 657 # Number of Nop instructions committed
|
|
|
|
|
system.cpu.comStores 925 # Number of Store instructions committed
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
|
|
|
|
|
system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread)
|
|
|
|
|
system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 4892000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000 # average WriteReq mshr miss latency
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 3601000 # number of WriteReq miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3409000 # number of WriteReq MSHR miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 56245.033113 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 8493000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 8040000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.overall_hits 1938 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 8493000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.overall_misses 151 # number of overall misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 8040000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.overall_hits 5571 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.overall_misses 303 # number of overall misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 13 # number of replacements
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 5571 # Total number of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed
|
|
|
|
|
system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread)
|
|
|
|
|
system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52192.307692 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40153.846154 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 678500 # number of UpgradeReq miss cycles
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 522000 # number of UpgradeReq MSHR miss cycles
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 17584000 # number of demand (read+write) MSHR miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 439 # number of overall misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 17584000 # number of overall MSHR miss cycles
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.numCycles 58414 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.runCycles 11845 # Number of cycles cpu stages are processed.
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
|
|
|
|
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed.
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed.
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed.
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed.
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed.
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed.
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed.
|
2010-02-01 00:31:28 +01:00
|
|
|
system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed.
|
2010-06-25 23:42:55 +02:00
|
|
|
system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
2009-05-13 07:55:04 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
